computer-architecture

问题 Closed . This question needs to be more focused. It is not currently accepting answers. Want to improve this question? Update the question so it focuses on one problem only by editing this post. Closed 3 years ago . Prelude: This is admittedly a fairly broad question regarding computer architecture, but one that I hear from others and wonder about quite often myself. I also don't think that there is a direct or quick answer to this. However, I was hoping someone well-versed in systems

问题 The normal answers to why data alignment is to access more efficiently and to simplify the design of CPU. A relevant question and its answers is here. And another source is here. But they both do not resolve my question. Suppose a CPU has a access granularity of 4 bytes. That means the CPU reads 4 bytes at a time. The material I listed above both says that if I access a misaligned data, say address 0x1, then the CPU has to do 2 accesses (one from addresses 0x0, 0x1, 0x2 and 0x3, one from

问题 i can't understand the two lines at the end of this code input [15:0] offset ; output [31:0] pc; output [31:0] pc_plus_4; reg [31:0] pc; wire [31:0] pcinc ; assign pcinc = pc +4 ; assign pc_plus_4 = {pc[31],pcinc}; assign branch_aadr = {0,pcinc + {{13{offset[15]}},offset[15:0],2'b00}}; 回答1: If you are unfamiliar with curly braces {} , they are concatenation operators. You can read about them in the IEEE Std for Verilog (for example, 1800-2009, Section 11.4.12). assign pc_plus_4 = {pc[31]

问题 I am doing a practice question from Question 7 Shouldn't the address I highlighted be x3307, not x3308? The way I reasoned this out was that (PC before 2nd instruction) = (PC after 1st instruction). The PC after 1st instruction is x3301. Therefore when the second instruction executes, the PC, x3301 will be incremented by 6 to x3307. Does everyone agree? Or did I miss something and R3 should actually store x3308? 回答1: PC-relative offsets are applied on top of the already incremented PC, that

问题 I am doing a practice question from Question 7 Shouldn't the address I highlighted be x3307, not x3308? The way I reasoned this out was that (PC before 2nd instruction) = (PC after 1st instruction). The PC after 1st instruction is x3301. Therefore when the second instruction executes, the PC, x3301 will be incremented by 6 to x3307. Does everyone agree? Or did I miss something and R3 should actually store x3308? 回答1: PC-relative offsets are applied on top of the already incremented PC, that

问题 I have the following specifications of an ARM based SoC: L1 Data cache = 32 KB, 64 B/line, 2-WAY, LRU L2 Cache = 1 MB, 64 B/line, 16-WAY L1 Data TLB (for loads): 32 entries, fully associative L2 Data TLB: 512 entries, 4-WAY PDE Cache: 16 entries (one entry per 1 MB of virtual space) And I wonder what is the PDE cache? I guess it's something similar to TLB, but I'm not sure. Answer It seems that PDE (Page Directory Entry) is Intermediate table walk cache which indeed can be implemented

问题 What do we mean by the pointer based array access in MIPS? 回答1: There is an additional possible meaning or implication to "pointer based array access": You may have a pointer to an array, rather than an array at a fixed address. Actually, in C/C++, a "pointer to an array" is really usually just a pointer to the first element of the array. Basically, you have an array that is a parameter to a function, or a pointer to an array that is a member of a struct or class: void Foo(char a[]); /*or*/

问题 Today I got a different understand with my professor on the Parallel Programming class, about what is "false sharing". What my professor said makes little sense so I pointed it out immediately. She thought "false sharing" will cause a mistake in the program's result. I said, "false sharing" happens when different memory address are assigned to the same cache line, writing data to one of it will cause another being kicked out of the cache. If the processors write between the two false sharing

问题 I am a little stuck because I cannot find anything which covers the "data" part of the cache, everything that I have googled deals 99.9% with the addressing of cache. The question I was asked is worded as such Contrast the difference between "data bit" capacity and "overhead bit" size for the two caches. I don't want the answer so I am not going to post the actual set sizes and what not, I am just looking for a direction to maybe a website or an explanation of how to "contrast" the two. Any

问题 In a multi-processor architecture, how are registers organized? For example, in a 4 cores processor, a minimum of 4 processes can run at a time. How are stack pointer, program status registers and program counter organized? What about other general purpose registers? My guess is, each core will have a separate set of registers. 回答1: Imagine 4 completely separate computers, each with a single-core CPU. A 4-core computer is like that; except: All CPUs share the same physical address space (and