computer-architecture

问题 Since current x86_64 implementations are only capable of a forty eight bit "virtual" address space to reduce MMU complexity, could the top sixteen bits be used to implement security tag data. Do the current implementations restrict this (even know the IP and other segment registers are a full sixty four bits) usage and restrict the top sixteen bits of pointers to only contain virtual addresses and not other data? 回答1: No, you cannot. The top 16 bits are currently required to all be the same

问题 Is it possible to perform floating point operations in an embedded processor that does not have a Floating Point Unit? 回答1: Yes, you just have to do it in software. Your compiler may provide support, or you may need to roll your own. There are freely-available implementations, too. 回答2: Yes, e.g. early Linux kernels did emulate i387 floating point instructions in the kernel. It was rather slow, but allowed you to use the same binary on computers with and without a floating point unit. 来源：

问题 Please see below a question regarding word sizes in various instruction set architectures, and how that ties to assembly languages. Thank you for any and all help. First a few facts (please correct me if any of these are wrong). The word size of a processor architecture indicates (EDIT: Some of these were wrong, please see Seva's post below) : The largest size of each register The largest size of each memory address (amount of memory that can be addressed) The largest integer the CPU can

问题 This code fragment is extracted from an Android crash report on a Samsung Tab S: Build fingerprint: 'samsung/chagallwifixx/chagallwifi:5.0.2/LRX22G/T800XXU1BOCC:user/release-keys' Revision: '7' ABI: 'arm' r0 a0d840bc r1 a0dcb880 r2 00000001 r3 a0d840bc r4 a0dc3c4c r5 00000000 r6 a066d200 r7 00000000 r8 32d68f40 r9 a0c359a8 sl 00000014 fp bef3ba84 ip a0dc3fb8 sp bef3ba10 lr a0c35a0c pc a0c34bc8 cpsr 400d0010 r0 through r9 are pretty clearly general purpose registers, sp ( r13 ) is the stack

问题 I am trying to understand how a virtual machine monitor (VMM) virtualizes the CPU. My understanding right now is that the CPU issues a protection fault interrupt when a privileged instruction is about to be executed while the CPU is in user mode. In high level languages like C, privileged instructions are wrapped inside system calls. For example, when an application needs the current date and time (instructions that interact with I/O devices are privileged), it calls a certain library

问题 I am trying to understand how a virtual machine monitor (VMM) virtualizes the CPU. My understanding right now is that the CPU issues a protection fault interrupt when a privileged instruction is about to be executed while the CPU is in user mode. In high level languages like C, privileged instructions are wrapped inside system calls. For example, when an application needs the current date and time (instructions that interact with I/O devices are privileged), it calls a certain library

问题 I'm looking at the five stages MIPS pipeline (ID,IF,EXE,MEM,WB) in H&P 3rd ed. and it seems to me that the branch decision is resolved at the stage of ID so that while the branch instruction reaches its EXE stage, the second instruction after the branch can be executed correctly (can be fetched). But this leaves us the problem of possibly still wasting the 1st instruction soon after the branch instruction. I also encountered the concept of branch delay slot, which means you want to fill the

问题 The Intel core i7 has per-core L1 and L2 caches, and a large shared L3 cache. I need to know what kind of an interconnect connects the multiple L2s to the single L3. I am a student, and need to write a rough behavioral model of the cache subsystem. Is it a crossbar? A single bus? a ring? The references I came across mention structural details of the caches, but none of them mention what kind of on-chip interconnect exists. Thanks, -neha 回答1: Modern i7's use a ring. From Tom's Hardware:

问题 Why do computer use Hex Number System at assembly language? Why don't they use any other number system like binary, octal, decimal? What thing forced computer designer to use hex system at assembly? Why it looked so beneficial to them? 回答1: Well it doesn't make a difference how you represent them but as we know that humans don't understand binary numbers, they are only to make the computer's life easier as it works on only two states true and false. So in order to make binary numbers

问题 Why do computer use Hex Number System at assembly language? Why don't they use any other number system like binary, octal, decimal? What thing forced computer designer to use hex system at assembly? Why it looked so beneficial to them? 回答1: Well it doesn't make a difference how you represent them but as we know that humans don't understand binary numbers, they are only to make the computer's life easier as it works on only two states true and false. So in order to make binary numbers