Guidance on very shallow embedding VHDL in AGDA
问题 for my project in Programming Languages I am doing a very shallow and simple embedding VHDL digital circuits in agda. The aim is to write the syntax, static semantics, dynamic semantics and then write some proofs to show our understanding of the material. Up till now I have written the following code: data Ckt : Set where var : String → Ckt bool : Bool → Ckt empty : Ckt gate : String → ℕ → ℕ → Ckt -- name in out series : String → Ckt → Ckt → Ckt -- name ckt1 ckt2 parallel : String → Ckt → Ckt