Can someone explain the following load and store instructions as part of the ARM ISA?

问题

I'm just starting to learn ARM and I'm having trouble understanding what the load and store instructions do exactly.

Load instructions:

ldrsb
ldrb
ldrsh
ldrh
ldr

Store instructions:

strb
strh
str

What does it mean to "load halfword" signed or unsigned? Or to "load byte" signed or unsigned? What is the difference between signed and unsigned, and in what particular applications would some of the load/store instructions be practical to use? All in all, I'm looking for an intuitive understanding of what these instructions do, as I'm still confused about how they work and what their purposes are.

回答1:

When talking ARM a "word" is 32 bits, a "halfword" is 16 bits, and a "byte" is 8 bits. If you read the instruction set documentation in the ARM Architectural Reference Manual (just get the one for ARMv5 if you dont know which one to get, infocenter.arm.com) you will see that a ldrb loads the byte into the lower 8 bits of the destination register padding the upper 24 bits to zeros. A ldrsb will sign extend instead of pad with zeros. Same goes for halfword.

if you have code like this:

char a,b,c;
...
c = a+b;
if(c<0)
{
}

And either a or b or both were in memory at the time that you needed to do this addition then you would ideally want to do a sign extended (assuming you have told your compiler that char is signed) load to save instructions sign extending the registers so you can perform the math and have the flags set right for the comparison.

From the ARM ARM.

LDRSB (Load Register Signed Byte) loads a byte from memory, sign-extends it to form a 32-bit word, and writes the result to a general-purpose register.

LDRB (Load Register Byte) loads a byte from memory, zero-extends it to form a 32-bit word, and writes the result to a general-purpose register.

回答2:

ARM is a RISC (Reduced Instruction Set Computing) architecture, meaning memory must be moved into and out of registers using the instructions you're referring to, load and store instructions.

Load instructions take a single value from memory and write it to a general purpose register. Store instructions read a value from a general purpose register and store it in to memory.

Most Often Used Load/Store Instructions

Loads            Stores      Size and Type
LDR              STR         Word (32 bits)
LDRB             STRB        Byte (8 bits)
LDRH             STRH        Halfword (16 bits)
LDRSB                        Signed byte
LDRSH                        Signed halfword
LDM              STM         Multiple words

(taken from ARM Assembly Language - William Hohl)

Load and store instructions (in general) come in the follow form:

LDR | STR {type}{cond}    Rt, [Rn {, #offset}]

(although there are some differences depending on the type of addressing mode you wish to use, but I won't go into that here, if you'd like to know about more addressing modes, you should check out 'ARM post-index and pre-index addressing')

The 'type' is optional and is described in the table above, where you can choose to work with halfwords, bytes as well as signed or unsigned bytes or halfwords. You also have the option to load or store multiple registers.

You also have the option of adding a condition code to the instruction (cond), which is used to set the condition flags held in the Current Program Status Register (CPSR) - if you'd like to know more about this, you can search for 'ARM conditional execution' and 'condition codes'.

In ARM you must supply the source/destination register AND you must also supply a register containing an address referencing a location in memory. This is because an ARM instruction is a fixed length (32 bits) and some of these bits need to be used for the instruction it's self, so it's impossible to encapsulate a 32 bit memory address within a 32 bit ARM instruction.

In the above example, 'Rt' is the register where the value you are loading from memory will land (or the register containing the value you are storing to memory, if you are performing a store). 'Rn' is the register containing the address. The square brackets are in place to tell the processor that we're working with a register that contains an address, that we're working with a pointer. The optional offset is present in case you'd like to offset by a specific amount from the base register (this is handy in all kinds of useful applications, but I won't cover them here).

I hope this has given you some insight into the way in which ARM's load and store instructions work! :)

来源：https://stackoverflow.com/questions/14430522/can-someone-explain-the-following-load-and-store-instructions-as-part-of-the-arm