Constant padding in Verilog

问题

Here is the example behavioral Verilog code in question

module constant;
    reg [7:0] foo;
    initial begin
        foo = 1'bz;
        $display("%H", foo);
    end
endmodule

Icarus Verilog gave me

$ iverilog -o constant constant.v
$ ./constant
0Z

However, according to this website (and the lecturer of an FPGA course I am taking),

If number is smaller than the size constant, then it will be padded to the left with zeros. If the most significant bit of a specified number has an unknown (x) or high-impedance (z) value, then that value will be used to pad to the left.

In that case, the output should be ZZ instead of 0Z. I am pretty sure this is due to a change in the specification (maybe it's ZZ in Verilog 1995 and 0Z in Verilog 2001, or whatever), but what are the standards that result in each behavior? I have tried searching online for the specification, but they don't seem to be freely available, like this one which requires purchasing or a subscription.

As a bonus, where can I find a summary of changes across various specifications of Verilog?

回答1:

SystemVerilog IEEE 1800-2017 says:

If the size of the unsigned number is smaller than the size specified for the literal constant, the unsigned number shall be padded to the left with zeros. If the leftmost bit in the unsigned number is an x or a z, then an x or a z shall be used to pad to the left, respectively. If the size of the unsigned number is larger than the size specified for the literal constant, the unsigned number shall be truncated from the left.

However, the number here is not smaller than the size constant - the size here is the "1" in 1'bz.

In terms of conversions of expression results, the standard says:

Automatic type conversions from a smaller number of bits to a larger number of bits involve zero extensions if unsigned or sign extensions if signed. Automatic type conversions from a larger number of bits to asmaller number of bits involve truncations of the most significant bits (MSBs).

As this is an unsigned expression and result, the 1'bz literal expression is then zero extended to fit the 8 bit size of foo.

IEEE 1800-2017 is free to download for everyone from the IEEE webiste.

回答2:

I believe you are confusing what happens with numeric literals (like 8'bz) versus values in an expression. Numeric literals will fill the specified z or z to the specified width. But once in an expression, unsigned values get 0 padded and signed values get padded as your lecturer said.

Only the latest version of the IEEE standard is freely available—older version must be purchased. This website shows recent changes to the SystemVerilog standard.

来源：https://stackoverflow.com/questions/61315969/constant-padding-in-verilog