问题
I am currently reading ARM Cortex M0+ User Guide on ARM website shown below
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/CHDBIBGJ.html
In User Manual, following paragraph is mentioned:
Interruptible-restartable instructions
The interruptible-restartable instructions are LDM, STM, PUSH, POP and, in 32-cycle multiplier implementations, MULS. When an interrupt occurs during the execution of one of these instructions, the processor abandons execution of the instruction. After servicing the interrupt, the processor restarts execution of the instruction from the beginning.
I am not able to understand how restartable instructions works? Can somebody explain me different phases (fetch, decode and execute) of Interruptible-restartable instructions with an example? what happens to instruction pipeline when interrupt comes?
回答1:
For an LDM, the execute stage is actually multiple cycles (at least one for each register).
This is where the simple fetch/decode/execute model starts to break down - execute is actually a non-trivial state machine which can often represent a single cycle, but has a handful of 'special' operations.
With Cortex M, even at a basic level, when an exception occurs, there is a whole lot more work to do other than just pointing fetch at the exception handler and waiting for execute to become free after breaking out of its current instruction.
The key part to understanding both the uninterruptible and restartable instructions at a hardware level is that they are controlled by the architectural registers, and there is not a lot of intermediate state. Where there is intermediate state, it is stored in EPSR.ICI. There is also some intermediate register storage used for things like multiplication intermediate results so the architectural registers can be recovered without corruption.
As to why the architecture goes to the effort of supporting restartable or continuable instructions (as mentioned in the comments), this is specifically to improve interrupt latency (which is one of the key Cortex-M features). For a single load or store, the programmer generally has enough control over not risking too long a data interface stall when interrupt latency is critical, and there should not be too much impact on the 12 cycle latency. For a load/store multiple, the delay can be significant (and from a program point of view, something like a stack push is of no value when an exception is pending since the handler will itself take care of the immediate context save requirements). Since these processors typically only have a single data memory interface, the microcoded exception stacking can't take place in parallel with completing the remaining beats of a load/store multiple.
There is a trade off with multi-cycle instructions which are simply abandoned, instructions which are paused to continue later, and instructions which must complete. As a consequence of the bus interface, once a transfer has started, it must complete. Continuable instructions are not atomic, and restartable instructions can result in repeated accesses to the same address (so these must be avoided when writing to peripheral fifos and the like). All of this extra complication is still justified for the target application by maintaining good interrupt performance, and usually not requiring the programmer to worry about the precise details. The alternative would be to use individual LDM everywhere which is inefficient from a code density point of view (and potentially performance depending on the uArch/system).
来源：https://stackoverflow.com/questions/31114349/what-is-interruptible-restartable-instructions-in-arm-cortex-m0-m0