手册UG901,对vivado可综合的语句支持进行了描述，HDL包括：verilog-2001，system-verilog，VHDL；
verilog-2001扩展了对task和function的支持。
ug901手册中，章节7对支持的语法进行详细描述。
1 Filename: functions_1.v
2 //
3 // An example of a function in Verilog
4 //
5 // File: functions_1.v
6 //
7 module functions_1 (A, B, CIN, S, COUT);
8 input [3:0] A, B;
9 input CIN;
10 output [3:0] S;
11 output COUT;
12 wire [1:0] S0, S1, S2, S3;
13 function signed [1:0] ADD;
14 input A, B, CIN;
15 reg S, COUT;
16 begin
17 S = A ^ B ^ CIN;
18 COUT = (A&B) | (A&CIN) | (B&CIN);
19 ADD = {COUT, S};
20 end
21 endfunction
22
23 assign S0 = ADD (A[0], B[0], CIN),
24 S1 = ADD (A[1], B[1], S0[1]),
25 S2 = ADD (A[2], B[2], S1[1]),
26 S3 = ADD (A[3], B[3], S2[1]),
27 S = {S3[0], S2[0], S1[0], S0[0]},
28 COUT = S3[1];
29 endmodule
1 Filename: task_1.v
2 // Verilog tasks
3 // tasks_1.v
4 //
5 module tasks_1 (A, B, CIN, S, COUT);
6 input [3:0] A, B;
7 input CIN;
8 output [3:0] S;
9 output COUT;
10 reg [3:0] S;
11 reg COUT;
12 reg [1:0] S0, S1, S2, S3;
13
14 task ADD;
15 input A, B, CIN;
16 output [1:0] C;
17 reg [1:0] C;
18 reg S, COUT;
19 begin
20 S = A ^ B ^ CIN;
21 COUT = (A&B) | (A&CIN) | (B&CIN);
22 C = {COUT, S};
23 end
24 endtask
25
26 always @(A or B or CIN)
27 begin
28 ADD (A[0], B[0], CIN, S0);
29 ADD (A[1], B[1], S0[1], S1);
30 ADD (A[2], B[2], S1[1], S2);
31 ADD (A[3], B[3], S2[1], S3);
32 S = {S3[0], S2[0], S1[0], S0[0]};
33 COUT = S3[1];
34 end
35
36 endmodule
1 Filename: asym_ram_tdp_read_first.v
2 // Asymetric RAM - TDP
3 // READ_FIRST MODE.
4 // asym_ram_tdp_read_first.v
5
6 module asym_ram_tdp_read_first
7 (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
8
9 parameter WIDTHB = 4;
10 parameter SIZEB = 1024;
11 parameter ADDRWIDTHB = 10;
12 parameter WIDTHA = 16;
13 parameter SIZEA = 256;
14 parameter ADDRWIDTHA = 8;
15
16 input clkA;
17 input clkB;
18 input weA, weB;
19 input enaA, enaB;
20 input [ADDRWIDTHA-1:0] addrA;
21 input [ADDRWIDTHB-1:0] addrB;
22 input [WIDTHA-1:0] diA;
23 input [WIDTHB-1:0] diB;
24 output [WIDTHA-1:0] doA;
25 output [WIDTHB-1:0] doB;
26
27 `define max(a,b) {(a) > (b) ? (a) : (b)}
28 `define min(a,b) {(a) < (b) ? (a) : (b)}
29
30 function integer log2;
31 input integer value;
32 reg [31:0] shifted;
33 integer res;
34 begin
35 if (value < 2)
36 log2 = value;
37 else
38 begin
39 shifted = value-1;
40 for (res=0; shifted>0; res=res+1)
41 shifted = shifted>>1;
42 log2 = res;
43 end
44 end
45 endfunction
46
47
48
49 localparam maxSIZE = `max(SIZEA, SIZEB);
50 localparam maxWIDTH = `max(WIDTHA, WIDTHB);
51 localparam minWIDTH = `min(WIDTHA, WIDTHB);
52 localparam RATIO = maxWIDTH / minWIDTH;
53 localparam log2RATIO = log2(RATIO);
54 reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
55 reg [WIDTHA-1:0] readA;
56 reg [WIDTHB-1:0] readB;
57
58 always @(posedge clkB)
59 begin
60 if (enaB) begin
61 readB <= RAM[addrB] ;
62 if (weB)
63 RAM[addrB] <= diB;
64 end
65 end
66
67 always @(posedge clkA)
68 begin : portA
69 integer i;
70 reg [log2RATIO-1:0] lsbaddr ;
71 for (i=0; i< RATIO; i= i+ 1) begin
72 lsbaddr = i;
73 if (enaA) begin
74 readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
75 if (weA)
76 RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
77 end
78 end
79 end
80
81 assign doA = readA;
82 assign doB = readB;
83 endmodule
veriilog对常量、结构和编译指令的支持：
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来源：oschina
链接：https://my.oschina.net/u/4276393/blog/3794751