Warning (10230): Verilog HDL assignment warning at top_fpga.v(319): truncated value with size 32 to match size of target (16)
警告(10230):Verilog HDL assignment Warning at top pga.v(319):大小为32的截断值以匹配目标大小(16)
因为没有指定位宽,所以系统提示默认为32位所以你将 fifo_cnt<= fifo_cnt + 1; 改为fifo_cnt<= fifo_cnt + 1'b1;就可以了。
来源:CSDN
作者:Steven&Aileen
链接:https://blog.csdn.net/qq_25144391/article/details/103800176