问题
Suppose the CPU modifies the value in location x+50 and does not flush it back to main memory(write-back).
Meanwhile, a device launches a DMA read request from x to x+100.
In that case, how the CPU is informed to flush back the dirty cache line?
回答1:
The DMA circuitry often works directly with the main memory without involving the CPU (and that's the main idea, to free the CPU from doing I/O that can be done elsewhere in the hardware and thus save CPU cycles). So, you may indeed run into cache coherency problems. Microsoft recommends flushing I/O buffers when using DMA.
But some systems do support cache coherency protocols between CPUs and DMA circuits much like between CPUs in multiprocessor systems. The ultimate answer depends on the actual hardware.
回答2:
There are three approaches I can think of:
- The memory is marked as un-cacheable,
- the DMA controller co-ordinates with the cache controller,
- the OS guarantees this will never happen, e.g. by ensuring the CPU-part of the process isn't running.
It depends on the hardware, and the capabilities of the OS.
Ensuring the process is not running isn't too weird on a multi-tasking OS, as DMA on memory owned by a process is likely triggered by the process doing a system call, e.g. a write. The process can be de-scheduled, and other processes run, until the DMA completes.
It may be too much of a constraint to wait for an I/O device to complete, so the DMA controller might be copying from the processes address space to a secondary buffer.
So if you have a case where this has happened, please outline the example, and the tests you've run.
来源：https://stackoverflow.com/questions/10139472/cache-coherence-issues-in-a-dma-context