Relocate the ARM exception vectors?

前提是你 提交于 2019-12-06 11:20:20

This is highly dependent on the core you're working with.

Cortex-M3 chips can change the base address using the Vector Table Offset Register (VTOR) in the System Control Block. Some implementations might restrict possible addresses.

Of the "traditional" chips (ARM7/9, Cortex-A/R), I think none allow you to specify an arbitrary base, although most of them can switch between 00000000 and FFFF0000, and a few allow to use the "start of RAM" address.

However, if the chip has MMU, you can usually map a RAM page at FFFF0000 and copy your handlers there. I believe that's what Linux does.

More over, if your processor have security extension, you can take use of VBAR(Vector Base Address Register)

MCR p15, 0, <Rt>, c12, c0, 0

See the B4.1.156 in ARM Architecture Reference Manual.

For a cortex-A9 processor this can be done by making use of the VBAR register in the Cp15 co-processor register. The purpose of the Vector Base Address Register is to hold the base address for the Monitor exception vector.

 MRC p15, 0, <Rd>, c12, c0, 0    ; Read Secure or Non-secure Vector Base Address Register
 MCR p15, 0, <Rd>, c12, c0, 0    ; Write Secure or Non-secure Vector Base Address Register

A system register VBAR specifies the base address of the vector table. VBAR can be changed from PL1 or higher. Like most system registers, VBAR is also banked when Security Extension (TrustZone) is implemented.

易学教程内所有资源均来自网络或用户发布的内容,如有违反法律规定的内容欢迎反馈
该文章没有解决你所遇到的问题?点击提问,说说你的问题,让更多的人一起探讨吧!