constant drivers for net, vhdl shiftreg

问题

I'm trying to make a shiftregister in vhdl.

My issue is when I try to store values in the regisgter. This is the code that's causing trouble:

architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);

begin
    Rcv_adc:
    process(mclk, reset)
    begin
        if rising_edge(mclk) then
            if (reset = '0') then
                adc_out <= "0000000000000000";
            elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
                adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
            end if;
        end if;
    end process;
    adc_out <= adc_shfreg;  --compilation error here

the error i get is this:

Error (10028): Can't resolve multiple constant drivers for net "adc_out[13]" at chan_mod.vhd(40)

dont know if you need to see my ports, but here they are:

entity chan_mod is
    Port ( mclk : in std_LOGIC;
             reset : in std_logic;
             chan_on : in std_logic;
             chan_sel : in std_logic;
             adcdat : in std_logic;
             dacdat : out std_logic;
             bit_cntr : in std_logic_vector(4 DOWNTO 0);
             subcycle_cntr : in std_logic_vector(1 downto 0);
             dac_in : in std_logic_vector(15 DOWNTO 0);
             adc_out : out std_LOGIC_vector(15 DOWNTO 0);
             rd : in std_logic;
             wr : in std_logic);
end chan_mod;

(as you probably guessed a few of these are used later in the code and are therefore not in my code-sample)

回答1:

Your problem is that you're driving adc_out in the process as well as using a concurrent assignment. You should replace the assignment to adc_out in the reset case with an assignment to adc_shfreg.

architecture behave of chan_mod is
signal adc_shfreg : std_logic_vector(15 DOWNTO 0);
signal dac_shfreg : std_logic_vector(15 DOWNTO 0);

begin
    Rcv_adc:
    process(mclk, reset)
    begin
        if rising_edge(mclk) then
            if (reset = '0') then
                adc_out <= "0000000000000000"; <--- BAD! Replace adc_out with adc_shfreg
            elsif(chan_on = '1' AND subcycle_cntr = "01" AND chan_sel = '0' AND bit_cntr < 16) then
                adc_shfreg <= adc_shfreg(14 DOWNTO 0) & adcdat;
            end if;
        end if;
    end process;
    adc_out <= adc_shfreg;  --compilation error here

来源：https://stackoverflow.com/questions/12529551/constant-drivers-for-net-vhdl-shiftreg