Defining different parameter value for simulation and synthesis
问题 I'm using systemVerilog and I have a package that holds some of my modules parameter values (for example parameter SPI_RATE = 2_000_000; ). Is there any way I can set one value for simulation and a different one for synthesis? (I'm using ModelSim). For example I would like something like: if(IN_SIM) begin parameter SPI_RATE = 2_000_000; end else begin parameter SPI_RATE = 1_000_000; end Thanks! 回答1: Yes, that's possible. SystemVerilog supports conditional compiler directives such as `ifdef ,