sign-extension

问题 I get the Multiplication from 8bit and 8bit register. But, when you have one in 16 bit, and one in 8bit, how do we do the conversion before multiplying: Question : need to provide code fragments for 260*19, and print the results. I did: mov Ax,260 mov Al,19 cbw; Mul Ax PutInt Ax 回答1: mov Ax,260 mov Al,19 The AL register is the lowest half of the AX register. AX /-----------------\ MSB xxxx xxxx xxxx xxxx LSB \-------/ \-------/ AH AL The 2nd instruction mov al, 19 thus erroneously overwrites

问题 I get the Multiplication from 8bit and 8bit register. But, when you have one in 16 bit, and one in 8bit, how do we do the conversion before multiplying: Question : need to provide code fragments for 260*19, and print the results. I did: mov Ax,260 mov Al,19 cbw; Mul Ax PutInt Ax 回答1: mov Ax,260 mov Al,19 The AL register is the lowest half of the AX register. AX /-----------------\ MSB xxxx xxxx xxxx xxxx LSB \-------/ \-------/ AH AL The 2nd instruction mov al, 19 thus erroneously overwrites

问题 I am trying to create an Immediate Generator for RISC-V assembly but I have encountered with if statement. Here is my code in Verilog: module signextend(in, out, sel); parameter nin = 32; parameter nout = 32; input [nin-1:nin-25] in; input [2:0] sel; output [nout-1:0] out; if (sel == 3'b000) begin assign out[19:0] = in[31:12]; assign out[31:20] = {12{in[31]}}; end else if (sel == 3'b001) begin assign out[11:0] = in[31:20]; assign out[31:12] = {20{in[31]}}; end else if (sel == 3'b010) begin

来源： https://stackoverflow.com/questions/29668332/what-is-happening-in-this-assembly-code

来源： https://stackoverflow.com/questions/29668332/what-is-happening-in-this-assembly-code

问题 Assume $t2= 0x55555550 , then executing the following instruction: andi $t2, $t2, -1 $t2 becomes 0x0005550 This is confirmed by the MIPS emulator 1 However, it is not what I expected. I think the answer should be 0x55555550 & 0xFFFFFFFF = 0x55555550. I think the constant -1 was sign extended to 0xFFFFFFFF before the and logic. But it appears that the answer was 0x55555550 & 0x0000FFFF Why -1 is sign extended to 0x0000FFFF instead of 0xFFFFFFFF Footnote 1: Editor's note: MARS with "extended

问题 Here is a code in C++: void sign_extending(int x) { int r; // resulting sign extended number goes here struct {signed int x:5 ;} s; r = s.x = x; cout << r; } void Run() { int x=29; // this 29 is -3 ( 11101 ) in 5 bits // convert this from using 5 bits to a full int sign_extending(x); } The output of this code is -3. When i try to reproduce this code in python the bit field of 11101 is generated but when the answer is converted to an int the answer of 29 is given . the following is code of

问题 I'm reading about the Instruction Decode (ID) phase in the MIPS datapath, and I've got the following quote: "Once operands are known, read the actual data (from registers) or extend the data to 32 bits (immediates)." Can someone explain what the "extend the data to 32 bits (immediates)" part means? I know that registers all contain 32 bits, and I know what an immediate is. I just don't understand why you need to extend the immediate from 26 to 32 bits. Thanks! 回答1: On a 32-bit CPU, most of

问题 How can I fix the problem of moving 8 bit value to the BX register (16 bit)? mov al, 10h mov bx, al for this I get: operands do not match: 16 bit and 8 bit register 回答1: The answer depends on whether you want to zero extend or sign extend the value and on whether you can or cannot use instructions available starting with the 80386. For better performance, the 80386 or later code should be used if movzx and movsx are available. zero extend on an 8086 or 80286 Zero the upper half, then move to

问题 For x86 and x64 compilers generate similar zero/sign extend MOVSX and MOVZX. The expansion itself is not free, but allows processors to perform out-of-order magic speed up. But on RISC-V: Consequently, conversion between unsigned and signed 32-bit integers is a no-op, as is conversion from a signed 32-bit integer to a signed 64-bit integer. A few new instructions (ADD[I]W/SUBW/SxxW) are required for addition and shifts to ensure reasonable performance for 32-bit values. (C) RISC-V Spec But at