ptx

I have the following function with inline assembly that works fine on debug mode in 32 bit Visual Studio 2008: __device__ void add(int* pa, int* pb) { asm(".reg .u32 s<3>;"::); asm(".reg .u32 r<14>;"::); asm("ld.global.b32 s0, [%0];"::"r"(&pa)); //load addresses of pa, pb printf(...); asm("ld.global.b32 s1, [%0];"::"r"(&pb)); printf(...); asm("ld.global.b32 r1, [s0+8];"::); printf(...); asm("ld.global.b32 r2, [s1+8];"::); printf(...); ...// perform some operations } pa and pb are globally allocated on the device such as __device__ int pa[3] = {0, 0x927c0000, 0x20000011}; __device__ int pb[3] =

I need to modify the PTX code and compile it directly. The reason is that I want to have some specific instructions right after each other and it is difficult to write a cuda code that results my target PTX code, So I need to modify ptx code directly. The problem is that I can compile it to (fatbin and cubin) but I dont know how to compile those (.fatbin and .cubin) to "X.o" file. Robert Crovella There may be a way to do this with an orderly sequence of nvcc commands, but I'm not aware of it and haven't discovered it. One possible approach however, albeit messy, is to interrupt and restart the

I have following thrust::transform call. my_functor *f_1 = new my_functor(); thrust::transform(data.begin(), data.end(), data.begin(),*f_1); I want to detect it's corresponding kernel in PTX file. But there are many kernels containing my_functor in their mangled names. For example- _ZN6thrust6system4cuda6detail6detail23launch_closure_by_valueINS2_17for_each_n_detail18for_each_n_closureINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIiEEEESD_NS_9null_typeESE_SE_SE_SE_SE_SE_SE_EEEEjNS9_30device_unary_transform_functorI10my_functorEENS3_20blocked_thread_arrayEEEEEvT_

Is there any way on CUDA 2.0 devices to disable L1 cache only for one specific variable? I know that one can disable L1 cache at compile time adding the flag -Xptxas -dlcm=cg to nvcc for all memory operations. However, I want to disable cache only for memory reads upon a specific global variable so that all of the rest of the memory reads to go through the L1 cache. Based on a search I have done in the web, a possible solution is through PTX assembly code. Reguj As mentioned above you can use inline PTX, here is an example: __device__ __inline__ double ld_gbl_cg(const double *addr) { double

I am still not sure how to properly specify the architectures for code generation when building with nvcc. I am aware that there is machine code as well as PTX code embedded in my binary and that this can be controlled via the controller switches -code and -arch (or a combination of both using -gencode ). Now, according to this apart from the two compiler flags there are also two ways of specifying architectures: sm_XX and compute_XX , where compute_XX refers to a virtual and sm_XX to a real architecture. The flag -arch only takes identifiers for virtual architectures (such as compute_XX )

I've recently gotten my head around how NVCC compiles CUDA device code for different compute architectures. From my understanding, when using NVCC's -gencode option, "arch" is the minimum compute architecture required by the programmer's application, and also the minimum device compute architecture that NVCC's JIT compiler will compile PTX code for. I also understand that the "code" parameter of -gencode is the compute architecture which NVCC completely compiles the application for, such that no JIT compilation is necessary. After inspection of various CUDA project Makefiles, I've noticed the