Is there an execute-store data hazard in MIPS?
问题 On MIPS architecture with pipelining and forwarding: add $s0, $t1, $t2 sw $s0, 0($sp) The add instruction will have the result ready at step 3 (execute operation) however I presume that the sw instruction want the result at step 2 (Instruction decode & register read). There is a solved exercise in the book Computer Organization and Design by David A. Patterson: Find the hazards in the following code segment and reorder the instructions to avoid any pipeline stalls : lw $t1, 0($t0) lw $t2, 4(