neon

Originally the problem appeared when I tried to optimize an algorithm for neon arm and some minor part of it was taking 80% of according to profiler. I tried to test to see what can be done to improve it and for that I created array of function pointers to different versions of my optimized function and then I run them in the loop to see in profiler which one performs better: typedef unsigned(*CalcMaxFunc)(const uint16_t a[8][4], const uint16_t b[4][4]); CalcMaxFunc CalcMaxFuncs[] = { CalcMaxFunc_NEON_0, CalcMaxFunc_NEON_1, CalcMaxFunc_NEON_2, CalcMaxFunc_NEON_3, CalcMaxFunc_C_0 }; int N =

I'm trying to implement the checksum computation code(2's complement addition) for NEON, using intrinsic. The current checksum computation is being carried out on ARM. My implementation fetches 128-bits at once from the memory into NEON registers and does SIMD (addition), and result is folded to a 16-bit number from a 128-bit number. Everything looks to be working fine, but my NEON implementation is consuming more time that of the ARM version. ARM version takes: 0.860000 s NEON version takes: 1.260000 s Note: Profiled using utilities from "time.h" The checksum function called 10,000 times from

I have a ARM NEON Cortex-A8 based processor target. I was optimizing my code by making use of NEON. But when I compile my code I get this strange error. Don't know how to fix this. I'm trying to compile the following code (PART 1) using Code Sourcery (PART2) on my host. And I get this strange error (PART3). Am I doing something wrong here? Can anyone else compile this and see if they also get the same compilation error? The strange part is, in the code if I comment out the else if(step_size == 4) part of the code, then the error vanishes. But, sadly my optimization is not complete with out it,

I am trying the following assembly code: vclt.f32 q9,q0,#0 vst1.i32 q9,[r2:128] But if the condition is true, the corresponding element in q9 is set to negative one instead of positive one. What can I do to get a positive one ? This is normal for vector compare instructions, so you can use the compare result as a mask with AND or XOR instructions, or various other use-cases. You usually don't need a +1. If you want to count the number of elements that match, for example, just use a subtract instruction to subtract 0 or -1 from a vector accumulator. To get an integer +1, you could subtract it

I want to calculate the magnitude and the angle of 4 points using neon instructions SIMD and arm assembly. There is a built in library in most languages, C++ in my case, which calculates the angle (atan2) but for only one pair of floating point variables (x and y). I would like to exploit SIMD instructions that deal with q registers in order to calculate atan2 for a vector of 4 values. The accuracy is required not to be high, the speed is more important. I already have a few assembly instructions which calculate the magnitude of 4 floating-point registers, with acceptable accuracy for my

I have to translate the following instructions from SSE to Neon uint32_t a = _mm_cvtsi128_si32(_mm_shuffle_epi8(a,SHUFFLE_MASK) ); Where: static const __m128i SHUFFLE_MASK = _mm_setr_epi8(3, 7, 11, 15, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1); So basically I have to take 4th,8th,12th and 16th bytes from the register and put it into an uint32_t . Looks like a packing instruction (in SSE I seem to remember I used shuffle because it saves one instructions compared to packing, this example shows the use of packing instructions). How does this operation translate in Neon? Should I use