mmu

The user virtual address space for x86-64 with Linux is 47 bit long. Which essentially means that Linux can map a process with around ~128 TB virtual address range. However, what confuses me that x86-64 architecture supports ISA defined 4-level hierarchical page table (arranged as radix-tree) for each process. The root of the page table can only map up to 512 GB of contiguous virtual address space. So how Linux can support more than 512GB of virtual address range? Does it uses multiple page tables for each process? If yes, then for a process what should the CR3 (x86-64's register to contain

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: When I debug MMU in Cortex-A9 MPCore, I always see Domain Access Control Register , but, what does domain means ? up to 16 domains ? Anyone can give me a link to explain this ? 回答1: TL;DR The DACR not only decreases the context switch code path, but can also speed execution after the context switch occurs. There are several links which explain the specifics of Domain Access Control Register or DACR . For example ARM's Memory access permissions and domains . However, this page and many others don't explain why you might need this feature;

Ref. Linux kernel ARM Translation table base (TTB0 and TTB1) I have father doubt/query on topic discussed in previous link: 0 to 0xbfffffff is a lower part of memory (for user processes) and managed by the page table in TTB0, it contains the page-table of the current process Ref. arm/include/asm/pgtable-2level.h : PTRS_PER_PGD =2048, PTRS_PER_PMD =1, PTRS_PER_PTE =512 0xc0000000 to 0xffffffff is upper part (OS and memory-mapped I/O) of the address space managed/translated by the page table in TTBR1. TTB1 table is fixed in size and alignment (to 16k). Each level 1 entry of size is 32bits and

According to some tutorials, we will disable MMU and I/D-Caches at the beginning of bootlaoder. If I understand correctly, it aims to use the physical address directly in the program, so please correct me if I'm wrong. Thank you! Secondly, we do this to disable MMU and Caches: mrc P15, 0, R0, C1, C0, 0 bic R0, R0, #0x00002300 @ clear bits 13, 9:8 bic R0, R0, #0x00000087 @ clear bits 7, 2:0 orr R0, R0, #0x00000002 @ set bit 2 (A) Align orr R0, R0, #0x00001000 @ set bit 12 (I) I-Cache mcr P15, 0, R0, C1, C0, 0 D-Cache, MMU and Data Address Alignment Fault Checking have been disabled by clear

Is it possible to get list of translations (from virtual pages into physical pages) from TLB (Translation lookaside buffer, this is a special cache in the CPU). I mean modern x86 or x86_64; and I want to do it in programmatic way, not by using JTAG and shifting all TLB entries out. The linux kernel has no such dumper, there is page from linux kernel about cache and tlb: https://www.kernel.org/doc/Documentation/cachetlb.txt "Cache and TLB Flushing Under Linux." David S. Miller There was an such TLB dump in 80386DX (and 80486, and possibly in "Embedded Pentium" 100-166 MHz / " Embedded Pentium

ARM MIPS 安全性总览 基于trust zone构建，区分为一个安全世界与一个正常世界，正常世界不可以访问安全世界的存储空间等部件，正常世界信任安全世界，安全世界中的指令互相信任。 基于虚拟化CPU的硬件，允许存在多个域，并且每个域都是独立被保护的，互相不信任其他域中的软件或是数据，MIPS-VZ最多允许255个独立域。这些域运用于不同的模式下：内核模式以及用户模式。 ARMv8-M和MIPS-VZ都使用了额外的执行执行模式给与most trusted code以更多权限，同时减少less trusted code的权限 存储管理中的安全性 ARMv8-M使用了两个模块解决存储单元访问问题，分别是SAU（安全属性单元）以及MPU（存储保护单元）。SAU检查安全/不安全模式，然后MPU在不同模式下利用不同的权限访问，这两个单元基于地址比较器 是用了有如下两个特点的MMU：1.大系统区分为客人TLB和根TLB的两层TLB系统，分别给客户OS与内核软件使用。2.小系统区分为两级MMU，客人部分可以是一个完整的TLB也可以是一个固定映射转换单元，根部分将TLB拆成没有物理地址的部分，成为根保护单元(RPU). 这种MMU基于CAM(?),较好地提供了应用软件与操作系统之间的绝缘。 不同安全域之间的例程调用 ARMv8-M拥有一种不使用SMC(secure monitor call