microprocessors

I am getting Error while trying to disable Hardware prefetcher in my Core i7 system. I am following the method as per the link How do I programmatically disable hardware prefetching? In my system grep -i msr /boot/config-$(uname -r) CONFIG_X86_DEBUGCTLMSR=y CONFIG_X86_MSR=y CONFIG_SCSI_ARCMSR=m Here is my error message root@ ./rdmsr 0x1a0 850089 [root@ ./wrmsr -p 0 0x1a0 0x850289 (to disable hardware prefetcher in Core i7) wrmsr:pwrite: Input/output error I am getting same error for disabling Adjacent cache line prefetcher Any idea how to resolve this problem ? Thanks in advance . MSR

I watched a video on an 8-bit pc being fed a program - manually, using physics switches. The fed program was: MAIN: 0000 0001 0100 # 0 = LDA [4] 0001 0010 0101 # 1 = ADD [5] 0010 0101 0000 # 2 = OUT 0011 1111 0000 # 3 = HLT DATA: 0100 00001110 # 4 = #14 0101 00011100 # 5 = #28 What I want to know is how the computer, if it does, distinguishes between Data and Instructions, because there are no flags that divide data from instructions. 0001 0001 0010 may be interpreted as either: 1 = LDA [2] or: 1 = #10 Is it because while the program runs, addresses are treated as instructions. but because of

In the 8086 architecture, the memory space is 1 MiB in size and divided into logical segments of up to 64 KiB each. i.e. it has 20 address lines thus the following method is used: That the data segment register is shifted left 4 bits then added to the offset register My question is: How we do the shift operation although all the registers are only 16 bits Address translation is done internally by a special unit without using the registers available to user code to store intermediate results - it just fetches 16-bit values and does the translation inside - it is not reflected anywhere where the

I want to run sqlite in an embedded application. What's the bare minimum requirement to be able to run sqlite for maintaining a database? I'm looking at implementing the R*tree for spatial searches. It would be helpful if I could get an explanation justifying the requirements. Would a cortex M0/cortex M3 with with about 32kb of ram be enough? How much flash memory will i need? I'm looking at storing the database itself on an SD card. From About SQLite ...the size of the SQLite library can be reduced below 300KiB. SQLite can also be made to run in minimal stack space (4KiB) and very little heap

I need to understand memory fences in multicore machines. Say I have this code Core 1 mov [_x], 1; mov r1, [_y] Core 2 mov [_y], 1; mov r2, [_x] Now the unexpected results without memory fences would be that both r1 and r2 can be 0 after execution. In my opinion, to counter that problem, we should put memory fence in both codes, as putting it to only one would still not solve the problem. Something like as follows... Core 1 mov [_x], 1; memory_fence; mov r1, [_y] Core 2 mov [_y], 1; memory_fence; mov r2, [_x] Is my understanding correct or am I still missing something? Assume the architecture

I am unable to understand how does the direction flag work in x86 . The text in my lectures say that it increments or decrements the source or destination register but that does not make sense with its name. Can someone explain what it does? This flag is used in string operations, and specifies if strings begin at a low address and proceed to higher addresses or vice versa. For string instructions, ECX has the number of iterations, DS:ESI has the source address and ES:EDI has the destination (hence the s in ESI and the d in EDI ). After each iteration, ECX is decremented by one, and ESI and