lock-free

What happens when different CPU cores write to the same RAM address without synchronization?

折月煮酒 提交于 2019-12-19 10:35:06
问题 Let's assume that 2 cores are trying to write different values to the same RAM address (1 byte), at the same moment of time (plus-minus eta), and without using any interlocked instructions or memory barriers. What happens in this case and what value will be written to the main RAM? The first one wins? The last one wins? Undetermined behavior? 回答1: x86 (like every other mainstream SMP CPU architecture) has coherent data caches . It's impossible for two difference caches (e.g. L1D of 2

boost lockfree spsc_queue cache memory access

那年仲夏 提交于 2019-12-19 08:44:08
问题 I need to be extremely concerned with speed/latency in my current multi-threaded project. Cache access is something I'm trying to understand better. And I'm not clear on how lock-free queues (such as the boost::lockfree::spsc_queue) access/use memory on a cache level. I've seen queues used where the pointer of a large object that needs to be operated on by the consumer core is pushed into the queue. If the consumer core pops an element from the queue, I presume that means the element (a

boost lockfree spsc_queue cache memory access

岁酱吖の 提交于 2019-12-19 08:44:07
问题 I need to be extremely concerned with speed/latency in my current multi-threaded project. Cache access is something I'm trying to understand better. And I'm not clear on how lock-free queues (such as the boost::lockfree::spsc_queue) access/use memory on a cache level. I've seen queues used where the pointer of a large object that needs to be operated on by the consumer core is pushed into the queue. If the consumer core pops an element from the queue, I presume that means the element (a

How to guarantee 64-bit writes are atomic?

£可爱£侵袭症+ 提交于 2019-12-18 10:36:12
问题 When can 64-bit writes be guaranteed to be atomic, when programming in C on an Intel x86-based platform (in particular, an Intel-based Mac running MacOSX 10.4 using the Intel compiler)? For example: unsigned long long int y; y = 0xfedcba87654321ULL; /* ... a bunch of other time-consuming stuff happens... */ y = 0x12345678abcdefULL; If another thread is examining the value of y after the first assignment to y has finished executing, I would like to ensure that it sees either the value

how to put std::string into boost::lockfree::queue (or alternative)?

岁酱吖の 提交于 2019-12-18 07:37:11
问题 I'm trying to put std::string s into boost::lockfree::queue s so that my threads can update each other with new data. When I try to use boost::lockfree::queue<std::string> updated_data; , g++ says : In instantiation of 'class boost::lockfree::queue >': error: static assertion failed: (boost::has_trivial_destructor::value) error: static assertion failed: (boost::has_trivial_assign::value) I've been shown generally what these errors mean, but I have no hope of ever fixing this myself, as I'm

Trouble with boost::lockfree::queue in shared memory (boost 1.53, gcc 4.7.2 / clang 3.0-6ubuntu3)

柔情痞子 提交于 2019-12-18 05:48:06
问题 I have a problem with placing boost::lockfree::queue<<T, fixed_sized<false>, ..> in shared memory. I need it because I have to be able to insert more than 65535 messages into the queue, and fixed_sized queue is limited with 65535. The following code works properly (but capacity<...> option implies fixed_sized<true> ): typedef boost::interprocess::allocator< MessageT, boost::interprocess::managed_shared_memory::segment_manager> ShmemAllocator; typedef boost::lockfree::queue< MessageT, boost:

Why does a std::atomic store with sequential consistency use XCHG?

六眼飞鱼酱① 提交于 2019-12-18 05:12:39
问题 Why is std::atomic's store: std::atomic<int> my_atomic; my_atomic.store(1, std::memory_order_seq_cst); doing an xchg when a store with sequential consistency is requested? Shouldn't, technically, a normal store with a read/write memory barrier be enough? Equivalent to: _ReadWriteBarrier(); // Or `asm volatile("" ::: "memory");` for gcc/clang my_atomic.store(1, std::memory_order_acquire); I'm explicitly talking about x86 & x86_64. Where a store has an implicit acquire fence. 回答1: mov -store +

Is std::ifstream thread-safe & lock-free?

独自空忆成欢 提交于 2019-12-18 05:11:55
问题 I intend to perform opening for reading a single file from many threads using std::ifstream. My concern is if std::ifstream is thread-safe & lock-free? More details: I use g++ 4.4 on Ubuntu & Windows XP, 4.0 on Leopard. Each thread creates its own instance of std::ifstream Thanks in advance! 回答1: That is implementation defined. Standard C++ says absolutely nothing about threading, and therefore any assumptions about threads inherently invoke unspecified or implementation defined behavior. We

Lock free multiple readers single writer

∥☆過路亽.° 提交于 2019-12-18 04:21:53
问题 I have got an in memory data structure that is read by multiple threads and written by only one thread. Currently I am using a critical section to make this access threadsafe. Unfortunately this has the effect of blocking readers even though only another reader is accessing it. There are two options to remedy this: use TMultiReadExclusiveWriteSynchronizer do away with any blocking by using a lock free approach For 2. I have got the following so far (any code that doesn't matter has been left

How can I write a lock free structure?

给你一囗甜甜゛ 提交于 2019-12-17 23:22:11
问题 In my multithreaded application and I see heavy lock contention in it, preventing good scalability across multiple cores. I have decided to use lock free programming to solve this. How can I write a lock free structure? 回答1: Short answer is: You cannot. Long answer is: If you are asking this question, you do not probably know enough to be able to create a lock free structure. Creating lock free structures is extremely hard, and only experts in this field can do it. Instead of writing your own