RISC-V Interrupt Handling Flow
问题 I am looking for how a RISC-V processor processes interrupt requests. I looked at the Instruction Set Manuals and information on the internet. The focus is on explaining exactly what the title sets: the instruction set. In my view, how interrupts are handled is a question of what is called the "programmer's model" of the processor. It does not clearly fit into a document about an instruction set, because parts of interrupt processing are not expressed in instructions. Clearly, jumping into an