fsm

问题 I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz. This counter is built in one state of FSM and is started by pushing a button on DE2 board. Firstly, whole system is in IDLE state and if I push this button, state is changed to COUNTING and counter begin to be incremented and his current value is shown on LED display. After it reach value of modulo, the state COUNTING is

问题 I am planning to use XState for managing states in the backend of my application. When an api is called, a function will be called on successful state change. The result of the function call has to be returned as response of the api. // Returns a Promise, e.g.: // { // id: 42, // name: 'David', // friends: [2, 3, 5, 7, 9] // friend IDs // } function getUserInfo(context) { return fetch('/api/users/#{context.userId}').then(response => response.json() ); } // Returns a Promise function

问题 Recommendations for languages with native (so no FSM generation tools) support for state machine development and execution and passing of messages/signals. This is for telecoms, e.g implementation of FSMs of this level of complexity. I have considered Erlang, but would love some feedback, suggestions, pointer to tutorials, alternatives, particularly Java based frameworks. Maybe Scala? Open source only. I'm not looking for UML or regular expression related solutions. As this is for the

问题 I would like to implement a FSM/"pushdown automaton" parser for this syntax: parser with scopes and conditionals which has already been "lexed" into Finite State Machine parser I have the following: class State { public: virtual State* event( const string &token ); State* deleteDaughter(); private: A* m_parent; A* m_daughter; } class SomeState : public State { public: State* event( const std::string &token ); } With B 's event() doing (after many if-elseif's) return m_parent->deleteDaughter()

问题 I have a question about what seems to me odd behavior of an AGC/SPI controller I'm working on. It's done in Verilog, targeting a Xilinx Spartan 3e FPGA. The controller is a FSM that relies on external inputs to start. The state of the FSM is stored in state_reg which is not explicitly initialized, as I thought an uninitialized register would default to zero. When I implemented the controller the FSM would not run. Monitoring the SPI bus I observed no activity. To monitor the FSM i routed the

问题 I understand the reason and the proof why {a^n b^n | n >= 0} is NOT regular. Why is {a^nb^n | n >= 0} not regular? The solution of one of my exercises is: {a^n a^n | n >= 0} is regular. How can I prove this thesis? 回答1: Yes, Language {a n a n | n >= 0} is a regular language . To proof that certain language is regular, you can draw its dfa/regular expression. And you can drive do for this language as follows: Because " a n a n for n >= 0 " is same as " a 2n for n >=0", and that is "set of all

问题 I understand the reason and the proof why {a^n b^n | n >= 0} is NOT regular. Why is {a^nb^n | n >= 0} not regular? The solution of one of my exercises is: {a^n a^n | n >= 0} is regular. How can I prove this thesis? 回答1: Yes, Language {a n a n | n >= 0} is a regular language . To proof that certain language is regular, you can draw its dfa/regular expression. And you can drive do for this language as follows: Because " a n a n for n >= 0 " is same as " a 2n for n >=0", and that is "set of all

问题 would you have a hint at algorithm to convert any regular expression to a finite state machine. For instance, an algorithm parsing a regexp and adding states to the fsm appropriately? Any reference or deeper idea? I am writting this with Python Thanks and regards 回答1: Use Michael Sipser's Introduction to the Theory of Computation. Chapter 1 gives detailed algorithms for converting a regular expression to a deterministic or non-deterministic finite-state automaton (DFA or NFA), in the context

问题 In the Stack Overflow podcast #36 (http://blog.stackoverflow.com/2009/01/podcast-36/), this opinion was expressed: Once you understand how easy it is to set up a state machine, you’ll never try to use a regular expression inappropriately ever again. I've done a bunch of searching. I've found some academic papers and other complicated examples, but I'd like to find a simple example that would help me understand this process. I use a lot of regular expressions, and I'd like to make sure I never

问题 When I learnt how to express finite state machines in VHDL, it was with a two-process architecture. One process handles the clock/reset signals, and another handles the combinatorial logic of updating the state and output. An example is below. I've seen this style criticised (see the comments and answer to this question for example), but never in any detail. I'd like to know whether there are objective(ish) reasons behind this. Are there technical reasons to avoid this style? Xilinx'