Lexing The VHDL ' (tick) Token
问题 In VHDL it the ' character can be used to encapsulate a character token ie '.' or it can as an attribute separator (similarish to CPP's :: token) ie string'("hello") . The issue comes up when parsing an attribute name containing a character ie string'('a','b','c') . In this case a naive lexer will incorrectly tokenize the first '(' as a character, and all of the following actual character will be messed up. There is a thread in comp.lang.vhdl google group from 2007 which asks a similar