cortex-m

问题 I use GCC 5.2.0 to compile code for an EFM32 MCU (based on a Cortex-M core). I notice an awful increase in code size when I want to #include <iostream> . For example, let's compile the following code for an EFM32WG "Wonder Gecko" chip: #include "em_device.h" #include "em_chip.h" #include <iostream> int main(void) { CHIP_Init(); while (1) { } } This code will result in 172048 bytes of code, whereas without #include <iostream> it is only 1440 bytes. I usually just use cout for debug output (by

问题 I am confused with the clock system on my STM32F7 device (Cortex-M7 microcontroller from STMicroelectronics). The reference manual does not clarify the differences between these clocks sufficiently: SYSCLK HCLK FCLK The reference manual reads in chapter << 5.2 Clocks >> "The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock (HCLK) divided by 8." This statement contradicts the figure from CubeMX. Notice that in CubeMX I can choose myself the prescaler from

问题 [A lot of text incoming, since I want to detail my question as best as I can.] I'm in the process of optimizing hand-written ARM assembly code for a Cortex-M0. The board I'm using is the STMicro STM32F0Discovery, which has an STM32F051R8 controller. The controller is running at 48 MHz. Unfortunately, I'm getting some pretty strange cycle counts when doing optimizations. For example, adding a single nop into a loop in my code should add 2 cycles in total (looped 2 times). However, doing so

问题 [A lot of text incoming, since I want to detail my question as best as I can.] I'm in the process of optimizing hand-written ARM assembly code for a Cortex-M0. The board I'm using is the STMicro STM32F0Discovery, which has an STM32F051R8 controller. The controller is running at 48 MHz. Unfortunately, I'm getting some pretty strange cycle counts when doing optimizations. For example, adding a single nop into a loop in my code should add 2 cycles in total (looped 2 times). However, doing so

问题 Recently I've been trying to do FFT calculations on my STM32F4-Discovery evaluation board then send it to PC. I have looked into my problem - I think that I'm doing something wrong with FFT functions provided by manufacturer. I'm using CMSIS-DSP libraries. For now I've have been generating samples with code (if that works correct I'll do sampling by microphone). I'm using arm_rfft_fast_f32 as my data are going to be floats in the future, but results I get in my output array are insane (I

问题 I'm trying to debug an embedded project using remote GDB. My system: Target: ARM Cortex M0. SEGGER J-Link GDB Server V6.10 Command Line Version arm-none-eabi-gdb 7.10.1.20160616-cvs CLion 2016.2.2, Build #CL-162.1967.7 Ubuntu 16.04 I have the following in my .gdbinit file: target remote localhost:2331 #(I remove this line when debugging with CLion) set verbose on file "/path_to_output_file/blinky.elf" monitor reset break main The thing that has troubled me for days now, is that this works

问题 I'm trying to debug an embedded project using remote GDB. My system: Target: ARM Cortex M0. SEGGER J-Link GDB Server V6.10 Command Line Version arm-none-eabi-gdb 7.10.1.20160616-cvs CLion 2016.2.2, Build #CL-162.1967.7 Ubuntu 16.04 I have the following in my .gdbinit file: target remote localhost:2331 #(I remove this line when debugging with CLion) set verbose on file "/path_to_output_file/blinky.elf" monitor reset break main The thing that has troubled me for days now, is that this works

问题 My question is about some popular but not well documented code I have found in ARM CORTEX M startup files like this STM32. The 'pattern' is: .size X,.-X ,where X is a symbol or label. I have found this answer and understand how .size directive and dot special symbol work, but still complete line seems to do nothing to me. The result of the operation .-X isn't stored anywhere. Could anybody explain what the line does? 回答1: That is placed at the end of function X, and the size of the function

问题 I need to force IAR tp use certain Cortex-M0+ instruction in some part of my code while codding with C. Please do not offer pure asm functions or inline asm etc. I have managed to do this for 51 instruction but could not for ; ADR, BLX, RSBS, SBCS, SXTH instructions. Optimization is disabled for this function (#pragma optimization=none) I have tried many things by considering instruction behaviour. But IAR preferred to same function with different instructions. Did anyone else struggle with

问题 I need to force IAR tp use certain Cortex-M0+ instruction in some part of my code while codding with C. Please do not offer pure asm functions or inline asm etc. I have managed to do this for 51 instruction but could not for ; ADR, BLX, RSBS, SBCS, SXTH instructions. Optimization is disabled for this function (#pragma optimization=none) I have tried many things by considering instruction behaviour. But IAR preferred to same function with different instructions. Did anyone else struggle with