How to force IAR to use desired Cortex-M0+ instructions (optimization will be disabled for this func.)

问题

I need to force IAR tp use certain Cortex-M0+ instruction in some part of my code while codding with C.

Please do not offer pure asm functions or inline asm etc.

I have managed to do this for 51 instruction but could not for ; ADR, BLX, RSBS, SBCS, SXTH instructions.

Optimization is disabled for this function (#pragma optimization=none)

I have tried many things by considering instruction behaviour. But IAR preferred to same function with different instructions.

Did anyone else struggle with such a unnecessary thing before or has anyone an idea?

回答1:

Please do not offer pure asm functions or inline asm etc.

But these are the only solution to your problem that won't depend on compiler version.

You may have

managed to do this for 51 instruction

..but the next (major) compiler version could have a vastly different idea on how to generate instructions for your C code, even when the optimizer is off. BTDT for GCC.

Coding stuff in assembly language directly eliminates this compiler version dependecy altogether. You should even have some example code, as most C-startup (reset handler) code is shipped as assembly language file.

回答2:

Apart from BLX which isn't available on cortex-m this code may get you there. Maybe you have to turn on some optimizations.

char const * getstr(void)
{
    return "ADR";
}

long long llfunc(long long v1, long long v2)
{
    return v1 - v2;
}

int neg(int i)
{
    return -i;
}


void efunc(short);

void func(short s)
{
    efunc(s + 5);
}

来源：https://stackoverflow.com/questions/47673607/how-to-force-iar-to-use-desired-cortex-m0-instructions-optimization-will-be-di