compare-and-swap

问题 To start with, consider release semantics. If a data set is protected with a spinlock (mutex, etc. - no matters what exact implementation is used; for now, assume 0 means it's free and 1 - busy). After changing of the data set, a thread stores 0 to spinlock address. To force visibility of all previous actions before storing 0 to spinlock address, storing is executed with release semantics, that means all previous reads and writes shall be made visible to other threads before this storing. It

问题 So I read that in a 32bit machine, one can use the CAS operation with aligned 64bit blocks. Similarly, in a 64bit machine, one can use the CAS operation with aligned 128bit blocks. I'm using a 32bit machine so I tried the following: // sizeof(long long) is 8 bytes, so 64 bits long long y = 12; long long z = 12; long long x = 99; __sync_bool_compare_and_swap(&y, z, x); and the CAS succeeded changing the value of y to 99 . But then I tried using a char array[8]; (which size is 64 bits) instead

问题 Many of the C++11 CAS operations (e.g., atomic_compare_exchange_weak , atomic_compare_exchange_strong ) take two pointers and a value, i.e., like this: bool atomic_compare_exchange(T* pointer, T* expected, // pseudodeclaration! T desired); In contrast, the CAS operations from Microsoft, gcc, and Intel all take one pointer and two values: long InterlockedCompareExchange(long* pointer, long desired, // Microsoft long expected); int __sync_bool_compare_and_swap (T* pointer, T expected, // gcc

问题 Many of the C++11 CAS operations (e.g., atomic_compare_exchange_weak , atomic_compare_exchange_strong ) take two pointers and a value, i.e., like this: bool atomic_compare_exchange(T* pointer, T* expected, // pseudodeclaration! T desired); In contrast, the CAS operations from Microsoft, gcc, and Intel all take one pointer and two values: long InterlockedCompareExchange(long* pointer, long desired, // Microsoft long expected); int __sync_bool_compare_and_swap (T* pointer, T expected, // gcc

问题 Is this "compare and swap" statement always atomic regardless of engine (e.g. InnoDB or MyISAM)? : UPDATE tbl_name SET locked=1 WHERE id=ID AND locked <> 1; I ask this because I intend to use this statement to do pseudo row-level locking that is compatible with both transactional and non-transactional database tables. This is the method that is recommended for MyISAM, but I am uncertain as to whether this works for InnoDB since the documentation suggests using transactions instead. 回答1: Yes.

问题 I am trying to write a simple compare and swap inline assembly code. Here is my code #include <stdio.h> #include <stdlib.h> #include <stdint.h> static inline unsigned long cas(volatile unsigned long* ptr, unsigned long old, unsigned long _new) { unsigned long prev=0; asm volatile("lock cmpxchg8b %0;" : "=m"(prev) : "m"(*ptr),"a"(old),"c"(_new) ); return prev; } int main() { unsigned long *a; unsigned long b=5,c; a=&b; c=cas(a,b,6); printf("%lu\n",c); return 0; } This code should ideally print

问题 I am trying to implement a lock free list. For this project I need and atomic compare and swap instruction that can compare a 32 bit pointer to my 'node' struct. The node struct is as follows: typedef struct node { int data; struct node * next; struct node * backlink; }node_lf; I am using _sync_val_compare_and_swap() to perform compare and swap operation. My question is, can this function return a value other than int? This is what I am trying to do: node_lf cs(node_lf * address, cs_arg *old

问题 How do I steal 2 MSBs from an address to do an atomic operation? I'm trying to do a single word CAS An example public class Node { long key; long value; Node lchild; // format is flag1,flag2,address Node rchild; // format is flag1,flag2,address } public void createNode() { Node n1 = new Node(); //this should create a node with format 0,0,address1 } public void setFlag1(Node n1) { Now the new address should be in format 1,0,address1 } public void setFlag2(Node n1) { Now the new address should

问题 As Anthony Williams said: some_atomic.load(std::memory_order_acquire) does just drop through to a simple load instruction, and some_atomic.store(std::memory_order_release) drops through to a simple store instruction. It is known that on x86 for the operations load() and store() memory barriers memory_order_consume, memory_order_acquire, memory_order_release, memory_order_acq_rel does not require a processor instructions. But on ARMv8 we known that here are memory barriers both for load() and

问题 From what I understand, synchronized keyword syncs local thread cache with main memory. volatile keyword basically always reads the variable from the main memory at every access. Of course accessing main memory is much more expensive than local thread cache so these operations are expensive. However, a CAS operation use low level hardware operations but still has to access main memory. So how is a CAS operation any faster? 回答1: I believe the critical factor is as you state - the CAS