Can DMB instructions be safely omitted in ARM Cortex M4
I am going through the assembly generated by GCC for an ARM Cortex M4, and noticed that atomic_compare_exchange_weak gets two DMB instructions inserted around the condition (compiled with GCC 4.9 using -std=gnu11 -O2 ): // if (atomic_compare_exchange_weak(&address, &x, y)) dmb sy ldrex r0, [r3] cmp r0, r2 itt eq strexeq lr, r1, [r3] cmpeq.w lr, #0 dmb sy bne.n ... Since the programming guide to barrier instructions for ARM Cortex M4 states that: Omitting the DMB or DSB instruction in the examples in Figure 41 and Figure 42 would not cause any error because the Cortex-M processors: do not re