arm

问题 I want to run arm's linux system in gem5's fs mode,I download related files from this address: http://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries I was able to configure the correct file path, but finally got this output in the terminal2: [ 0.661620] No filesystem could mount root, tried: [ 0.661621] ext3 [ 0.661650] ext4`enter code here` [ 0.661663] ext2 [ 0.661676] vfat [ 0.661690] fuseblk [ 0.661703] [ 0.661728] Kernel panic - not syncing: VFS: Unable to mount root fs

问题 My program is supposed to ask for a single line of user input and then print out the number of characters in the string. As of now it is telling me there are 104 characters when I input hello followed by a segmentation fault. Here is my code: userInput: .asciz "\nEnter a string: " TemptRet: .word 10 inputBuffer: .skip 11 countMessage: .STRING "There are %d characters in: \"%s\".\n" .text .global main main: LDR R0, =courseStr BL puts countString: LDR R0, =userInput BL printf LDR R0, =TemptRet

问题 When I try to compile a trivial example test.c int main () { return 0; } for a cortex m7 target with hard float ABI by using the following invocation arm-none-eabi-gcc -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard --specs=nosys.specs test.c I get this error: /usr/lib/gcc/arm-none-eabi/6.3.1/../../../arm-none-eabi/bin/ld: error: /usr/lib/gcc/arm-none-eabi/6.3.1/../../../arm-none-eabi/lib/crt0.o: Conflicting CPU architectures 13/1 /usr/lib/gcc/arm-none-eabi/6.3.1/../../../arm-none-eabi/bin/ld

问题 I am relatively inexperienced with ARM assembly, and need help understanding a few lines. I have used Godbolt to compile C++ 11 code with the ARM gcc 8.2 compiler and got these lines of assembly: .L10: .word .LANCHOR0 I read that .LANCHOR0 are section anchors, but what does that mean? I understand that .word and .data can be used together to declare variables and assign values to memory spaces like this: .data ! start a group of variable declarations x: .word 23 ! int x = 23; But, what does

问题 I have an RPi4 and I'm trying to write some code in assembly to loop 1000 times. The code works fine when I set a lower number of loops, but when I try to set it 1001, gcc says: loop.s: Assembler messages: loop.s:15: Error: invalid constant (3e9) after fixup Here's the code: .data ms3: .asciz "%d\n" .text .global main .extern printf main: push {ip, lr} mov r1, #0 mov r5, #1001 loop1000: push {r1} ldr r0, =ms3 bl printf pop {r1} add r1, #1 cmp r1, r5 bne loop1000 pop {ip, pc} 回答1: Assembly

问题 I am relatively inexperienced with ARM assembly, and need help understanding a few lines. I have used Godbolt to compile C++ 11 code with the ARM gcc 8.2 compiler and got these lines of assembly: .L10: .word .LANCHOR0 I read that .LANCHOR0 are section anchors, but what does that mean? I understand that .word and .data can be used together to declare variables and assign values to memory spaces like this: .data ! start a group of variable declarations x: .word 23 ! int x = 23; But, what does

问题 I have a small application that uses a native ARM shared library ( .so ). When using Genymotion, I can successfuly install the ARM translation package (just by dropping the ZIP file) and the app runs fine on a x86-based emulator. Now I have the need to run the same app in a headless linux server, which is not supported by Genymotion. I downloaded the official google emulator and corresponding system image. After extracting the files from zip archive and uploading to /system partition, I can

问题 The Cortex-A57 Optimization Guide states that most integer instructions operating on 128-bit vector data can be dual-issued (Page 24, integer basic F0/F1, logical F0/F1, execution throughput 2). However with our internal (synthetic) benchmarks, throughput seems to be limited to exactly 1 128-bit neon integer instruction, even when there is plenty of instruction parallelism available (the benchmark was written with the intention to test whether 128-bit neon instructions can be dual-issued, so

问题 I had a problem with a static assert. The static assert was exactly like this: static_assert(std::atomic<bool>::is_always_lock_free); and the code failed on Raspberry Pi 3 (Linux raspberrypi 4.19.118-v7+ #1311 SMP Mon Apr 27 14:21:24 BST 2020 armv7l GNU/Linux). On the cppreference.com atomic::is_always_lock_free reference site it is stated that: Equals true if this atomic type is always lock-free and false if it is never or sometimes lock-free. The value of this constant is consistent with

问题 I am trying to implement the following pseudocode on a cortex-m3 controller, (STM32L151 in particular) void SysTick_Handler() { do_high_priority_periodic_tasks(); // not to be interrupted lower_interrupt_priority(); do_low_priority_periodic_tasks(); // these may be interrupted } In other words, run the first part with priority level 0, then somehow lower the current interrupt priority to 15, so that the rest could be preempted by other hardware interrupts. One idea is to move do_low_priority