If you see this popular pipeline diagram of ARM Cortex-A8 given in one of ARM presentations. It is clear that the instruction fetch stage takes 3 cycles, yet the first cycle is sort of discounted. But, why? Any thoughts?
Thank you...
From somewhat hidden paper on Cortex A8:
The fetch pipeline begins with the F0 stage where a new virtual address is generated. This address can either be a branch target address provided by a branch prediction for a previous instruction, or if there is no prediction made this cycle, the next address will be calculated sequentially from the fetch address used in the previous cycle. Note that the F0 Fetch stage is not counted as an official stage in the 13 stage main integer pipeline. This is because ARM processor pipelines have always counted stages beginning with the Instruction Cache access as the first stage.
来源：https://stackoverflow.com/questions/13106297/is-arm-cortex-a8-pipeline-13-stage-or-14-stage