问题
In the following sequence of MIPS instructions (entire program not shown):
DADDUI R1, R1, #-8
BNE R1, R2, Loop
I want to confirm the number of stalls required between the two instructions (in context of 5 stage MIPS pipeline - IF, ID/Reg, EX, MEM, WB) with and without forwarding.
My understanding:
(a) If there is no forwarding:
In this case, 2 stalls are required (in cycle 5, R1 can be read in the ID stage for second instruction using split phase access for registers)
(b) If there is forwarding:
In this case, no stalls are required (EX stage on second instruction in cycle 4 can get R1 - 8 forwarded from ALU result for EX stage of first instruction in cycle 3 ; this is assuming branch is checking for equality in EX stage).
Can someone please let me know if the above two answers are correct.
Thanks.
回答1:
You are correct. In doubt, always make timeline diagrams showing the various pipeline stages. In this case, pictorially, here's what happens:
Time moves from left to the right. The arrow crossing the table rows in the forwarding version shows where forwarding occurs.
Thus, for case (a), 2 cycles are wasted; for case (b), no cycles are wasted and the pipeline is not stalled.
来源：https://stackoverflow.com/questions/20755071/mips-pipeline-stalls-with-and-without-forwarding