问题
I'm writing cycle based logic simulation in C#. I want to simulate both combinational and sequential circuits. Combinational circuits are straightforward but sequential circuits give me trouble.
I want to detect oscillations and display appropriate warning message. Is there a simple way to check how many times a single gate can change its state and still leave the circuit stable?
I thought about 'minimum feedback arc set algorithm' but it seems to be an overkill. Many desktop applications does this fast so I doubt they're using it.
I also found paper advising the use of ternary logic (0, 1, unknown), and splitting algorithm in two parts - one initializing the circuit and one doing actual computations - but it was saying something like 'if algorithm A does not terminate the circuit has oscillations' which gives me nothing since there is no way to stop the clock cycle and warn the user.
Any ideas how applications like "Logisim" or "digital works" detect oscillations ?
回答1:
Verilator is a logic simulator that works by compiling synthesizable Verilog into C code.
It tries to construct an order of logic that will be guaranteed to be stable, but if it fails it emits some UNOPT and UNOPTFLAT warnings and simply repeats the simulation a number of times until nothing changes.
By default, 100 rounds are used before it reports a failure to converge, but this can be changed using argument converge-limit.
来源：https://stackoverflow.com/questions/19624134/how-to-detect-oscillations-in-gate-logic-simulations