问题
I'm new to Verilog and would really appreciate it if someone could help me with this.
I have a task written in a separate file - "task.v" :
module task_create();
task assign_inp;
reg a,b,c,d;
//details
endtask
endmodule
I have a module that is calling this task:
module tb();
`include "task.v"
assign_inp(a,b,c,d);
endmodule
When I execute this, I get this error:
Module definition task_create cannot nest into module tb
When I remove the module and endmodule in task.v, I get this error:
Task must be contained inside a module
Where am I going wrong? Thank you so much!
回答1:
Your task in in a module and so can only be seen in the module. What you can do is remove the module wrapper and just declare the task in a separate file.
task assign_inp;
reg a,b,c,d;
//details
endtask
You can include the task and you should be able to see the task.
Removing the modules works for me.
EDIT: You may need to declare the verilog file as a header file for the task
来源:https://stackoverflow.com/questions/37624934/how-to-call-tasks-from-a-separate-module-in-verilog