x86

问题 I have an OS project that I am working on and I am trying to call data that I have read from the disk in C with inline assembly. I have already tried reading the code and executing it with the assembly call instruction, using inline assembly. void driveLoop() { uint16_t sectors = 31; uint16_t sector = 0; uint16_t basesector = 40000; uint32_t i = 40031; uint16_t code[sectors][256]; int x = 0; while(x==0) { read(i); for (int p=0; p < 256; p++) { if (readOut[p] == 0) { } else { x = 1; //kprint

问题 Is it possible to have paging enabled in real mode, for example during BIOS execution. If it is enabled what is the use of having paging in real mode 回答1: No , From Intel Manual Vol 3A Chapter 2.5 Paging (bit 31 of CR0) — Enables paging when set; disables paging when clear. When paging is disabled, all linear addresses are treated as physical addresses. The PG flag has no effect if the PE flag (bit 0 of register CR0) is not also set ; setting the PG flag when the PE flag is clear causes a

问题 I have the following program written in nasm Assembly: section .text global _start: _start: ; Input variables mov edx, inLen mov ecx, inMsg mov ebx, 1 mov eax, 4 int 0x80 mov edx, 2 mov ecx, num1 mov ebx, 0 mov eax, 3 int 0x80 mov edx, inLen mov ecx, inMsg mov ebx, 1 mov eax, 4 int 0x80 mov edx, 2 mov ecx, num2 mov ebx, 0 mov eax, 3 int 0x80 ; Put input values in correct registers mov eax, [num1] sub eax, '0' ; convert char to num mov ebx, [num2] sub ebx, '0' ; convert char to num ; Perform

问题 TL;DR: In a producer-consumer queue does it ever make sense to put an unnecessary (from C++ memory model viewpoint) memory fence, or unnecessarily strong memory order to have better latency at the expense of possibly worse throughput? C++ memory model is executed on the hardware by having some sort of memory fences for stronger memory orders and not having them on weaker memory orders. In particular, if producer does store(memory_order_release) , and consumer observes the stored value with

问题 I have the following program written in nasm Assembly: section .text global _start: _start: ; Input variables mov edx, inLen mov ecx, inMsg mov ebx, 1 mov eax, 4 int 0x80 mov edx, 2 mov ecx, num1 mov ebx, 0 mov eax, 3 int 0x80 mov edx, inLen mov ecx, inMsg mov ebx, 1 mov eax, 4 int 0x80 mov edx, 2 mov ecx, num2 mov ebx, 0 mov eax, 3 int 0x80 ; Put input values in correct registers mov eax, [num1] sub eax, '0' ; convert char to num mov ebx, [num2] sub ebx, '0' ; convert char to num ; Perform

问题 TL;DR: In a producer-consumer queue does it ever make sense to put an unnecessary (from C++ memory model viewpoint) memory fence, or unnecessarily strong memory order to have better latency at the expense of possibly worse throughput? C++ memory model is executed on the hardware by having some sort of memory fences for stronger memory orders and not having them on weaker memory orders. In particular, if producer does store(memory_order_release) , and consumer observes the stored value with

问题 I have the following program written in nasm Assembly: section .text global _start: _start: ; Input variables mov edx, inLen mov ecx, inMsg mov ebx, 1 mov eax, 4 int 0x80 mov edx, 2 mov ecx, num1 mov ebx, 0 mov eax, 3 int 0x80 mov edx, inLen mov ecx, inMsg mov ebx, 1 mov eax, 4 int 0x80 mov edx, 2 mov ecx, num2 mov ebx, 0 mov eax, 3 int 0x80 ; Put input values in correct registers mov eax, [num1] sub eax, '0' ; convert char to num mov ebx, [num2] sub ebx, '0' ; convert char to num ; Perform

问题 TL;DR: In a producer-consumer queue does it ever make sense to put an unnecessary (from C++ memory model viewpoint) memory fence, or unnecessarily strong memory order to have better latency at the expense of possibly worse throughput? C++ memory model is executed on the hardware by having some sort of memory fences for stronger memory orders and not having them on weaker memory orders. In particular, if producer does store(memory_order_release) , and consumer observes the stored value with

问题 I am using NASM assembler on linux 64 bit. There is something with variables and registers I can't understand. I create a variable named "msg": msg db "hello, world" Now when I want to write to the stdout I move the msg to rsi register, however I don't understand the mov instruction bitwise ... the rsi register consists of 64 bit , while the msg variable has 12 symbols which is 8 bits each , which means the msg variable has a size of 12 * 8 bits , which is greater than 64 bits obviously. So

问题 I am using NASM assembler on linux 64 bit. There is something with variables and registers I can't understand. I create a variable named "msg": msg db "hello, world" Now when I want to write to the stdout I move the msg to rsi register, however I don't understand the mov instruction bitwise ... the rsi register consists of 64 bit , while the msg variable has 12 symbols which is 8 bits each , which means the msg variable has a size of 12 * 8 bits , which is greater than 64 bits obviously. So