x86

问题 I am trying to dive deep into volatile keyword in Java and setup 2 testing environments. I believe both of them are with x86_64 and use hotspot. Java version: 1.8.0_232 CPU: AMD Ryzen 7 8Core Java version: 1.8.0_231 CPU: Intel I7 Code is here: import java.lang.reflect.Field; import sun.misc.Unsafe; public class Test { private boolean flag = true; //left non-volatile intentionally private volatile int dummyVolatile = 1; public static void main(String[] args) throws Exception { Test t = new

问题 I am trying to dive deep into volatile keyword in Java and setup 2 testing environments. I believe both of them are with x86_64 and use hotspot. Java version: 1.8.0_232 CPU: AMD Ryzen 7 8Core Java version: 1.8.0_231 CPU: Intel I7 Code is here: import java.lang.reflect.Field; import sun.misc.Unsafe; public class Test { private boolean flag = true; //left non-volatile intentionally private volatile int dummyVolatile = 1; public static void main(String[] args) throws Exception { Test t = new

问题 I have read that there are some registers that an x86 CPU cannot modify while in user mode (I believe these registers are called "privileged registers"). But can an x86 CPU read the values of these registers while in user mode, or is even reading not allowed? 回答1: All the registers you'd normally use for computation can be read/written in any mode (GP integer, x87/MMX, XMM/YMM/ZMM and AVX512 k0-7 mask registers), but there are many registers that are basically mode/control settings. Some

问题 I am experiencing an issue where gdb is mapping a line number to the wrong memory address when adding a breakpoint. The following x86 Linux assembly program prints "hello". /* hello.s */ .section .data str: .ascii "hello\n" strlen = . - str .section .text print: pushl %ebp movl %esp, %ebp pushl %ebx movl $4, %eax movl $1, %ebx movl $str, %ecx movl $strlen, %edx int $0x80 popl %ebx movl %ebp, %esp popl %ebp ret .globl _start _start: call print movl $1, %eax movl $0, %ebx int $0x80 I compile it

问题 Are there any guidelines in x86-64 for when a function should abide by the System V guidelines and when it doesn't matter? This is in response to an answer here which mentions using other calling conventions for simplifying an internal/local function. # gcc 32-bit regparm calling convention is_even: # input in RAX, bool return value in AL not %eax # 2 bytes and $1, %al # 2 bytes ret # custom calling convention: is_even: # input in RDI # returns in ZF. ZF=1 means even test $1, %dil # 4 bytes.

问题 We are running some code in both VisualStudio process context (x86 context) and out of VisualStudio context (x64 context). I notice the following code provides a different result in both context (100000000000 in x86 and 99999997952 in x64) float val = 1000f; val = val * val; return (ulong)(val * 100000.0f); We need to obtain a ulong value from a float value in a reliable way, no matter the context and no matter the ulong value, it is just for hashing purpose. I tested this code in both x64

问题 Is TLB hierarchy inclusive on modern x86 CPU (e.g. Skylake, or maybe other Lakes)? For example, prefetchtn brings data to the level cache n + 1 as well as a corresponding TLB entry in DTLB. Will it be contained in the STLB as well? 回答1: AFAIK, on Intel SnB-family 2nd-level TLB is a victim cache for first-level iTLB and dTLB. (I can't find a source for this and IDK where I read it originally. So take this with a grain of salt . I had originally thought this was a well-known fact, but it might

问题 I am trying to figure out how the imul and idiv instructions of the 8086 microprocessor work. I know this: 1. mul and div are multiplications and division for unsigned numbers 2. imul and idiv, are also multiplications and divisions but for signed numbers I searched all the web, and what I just wrote above, that's the only info that I've found, but written in different ways. I have this: mov AX, 0FFCEh idiv AH Because ah it's a byte, AL=AX/AH (the result) and AH=remainder After the

问题 Let's say we have a processor with two cores (C0 and C1) and a cache line starting at address k that is owned by C0 initially. If C1 issues a store instruction on a 8-byte slot at line k , will that affect the throughput of the following instructions that are being executed on C1? The intel optimziation manual has the following paragraph When an instruction writes data to a memory location [...], the processor ensures that it has the line containing this memory location is in its L1d cache [.

问题 Each thread has its own stack to store local variables. But stacks are also used to store return addresses when calling a function. In x86 assembly, esp points to the most-recently allocated end of the stack. Today, most CPUs have stack grow negatively. This behavior enables arbitrary code execution by overflowing the buffer and overwriting the saved return address. If the stack was to grow positively, such attacks would not be feasible. Is it safer to have the call stack grow upwards? Why