x86

问题 I have the following source snippet from a book that I'm reading now. So I created an asm file and typed exactly. Then used nasm command ( nasm -f elf test.asm ) then tried to compile into an executable file by using gcc ( gcc test.o -o test ) then I get the following error. Error: ld: warning: ignoring file test.o, file was built for unsupported file format which is not the architecture being linked (x86_64) Source code: [BITS 16] [SECTION .text] START: mov dx, eatmsg mov ah, 9 int 21H mov

问题 So I am learning how x86 works and have come across people saying that it is byte-addressable, yet can read words, double words, etc. How does the processor decide which method to use and when? E.g. for accessing the next instruction and when a user wants to read/write to memory, which addressing mode is used? 回答1: Every memory access has an operand-size specified by the machine-code instruction. (Addressing mode isn't the right term: different addressing modes are different ways of

问题 I'm starting to use the Intel reference page to look up and learn about the op codes (instead of asking everything on SO). I'd like to make sure that my understanding is OK and ask a few questions on the output between a basic asm program and the intel instruction codes. Here is the program I have to compare various mov instructions into the rax -ish register (is there a better way to say "rax" and its 32- 16- and 8- bit components?): .globl _start _start: movq $1, %rax # move immediate into

问题 I'm starting to use the Intel reference page to look up and learn about the op codes (instead of asking everything on SO). I'd like to make sure that my understanding is OK and ask a few questions on the output between a basic asm program and the intel instruction codes. Here is the program I have to compare various mov instructions into the rax -ish register (is there a better way to say "rax" and its 32- 16- and 8- bit components?): .globl _start _start: movq $1, %rax # move immediate into

问题 What is the most efficient way in Intel x86 assembly to do the following operation ( a , b are 32-bit floats): From xmm1: [-, -, a, b] to xmm1: [a, a, b, b] I could not find any useful instructions. My idea is to copying a and b to other registers and then shift the xmm1 register 4 bytes and move a or b to the lowest 4 bytes. 回答1: You're looking for unpcklps xmm1, xmm1 (https://www.felixcloutier.com/x86/unpcklps) to interleave the low elements from a register with itself: low element ->

问题 In AT&T syntax instructions often have to be suffixed with the appropriate operand size, with q for operations on 64-bit operands. However in MMX and SSE there is also movq instruction, with the q being in the original Intel mnemonic and not an additional suffix. So how will this be represented in AT&T? Is another q suffix needed like movqq %mm1, %mm0 movqq %xmm1, %xmm0 or not? And if there are any other instructions that end like AT&T suffixes (like paddd , slld ), do they work the same way?

问题 In AT&T syntax instructions often have to be suffixed with the appropriate operand size, with q for operations on 64-bit operands. However in MMX and SSE there is also movq instruction, with the q being in the original Intel mnemonic and not an additional suffix. So how will this be represented in AT&T? Is another q suffix needed like movqq %mm1, %mm0 movqq %xmm1, %xmm0 or not? And if there are any other instructions that end like AT&T suffixes (like paddd , slld ), do they work the same way?

问题 I am reading Agner Fog's book on x86 assembly. I am wondering about how RIP-relative addressing works in this scenario. Specifically, assume my RIP offset is +1. This suggests the data I want to read is right next to this instruction in memory. This piece of data is likely already fetched into the L1 instruction cache. Assuming that this data is not also in the L1d, what exactly will happen on the CPU? Let's assume it's a relatively recent Intel architecture like Kaby Lake. 回答1: Yes, it's

问题 I'm on MAC OSX and I'm trying to call through assembly the execve syscall.. His opcode is 59 . In linux I have to set opcode into eax, then parameters into the others registers, but here I have to put the opcode into eax and push parameters into the stack from right to left. So I need execve("/bin/sh",NULL,NULL), I found somewhere that with assembly null=0, so I put null into 2nd and 3rd parameters. global start section .text start: jmp string main: ; 59 opcode ; int execve(char *fname, char

问题 I am reading Agner Fog's book on x86 assembly. I am wondering about how RIP-relative addressing works in this scenario. Specifically, assume my RIP offset is +1. This suggests the data I want to read is right next to this instruction in memory. This piece of data is likely already fetched into the L1 instruction cache. Assuming that this data is not also in the L1d, what exactly will happen on the CPU? Let's assume it's a relatively recent Intel architecture like Kaby Lake. 回答1: Yes, it's