x86

问题 This question is about the cmp instruction in assembly. I cannot understand how my books reasoning regarding the SF and OF flags. cmp vleft, vright According to my book: For signed integers, there are three flags that are important: the zero (ZF) flag, the overflow (OF) flag and the sign (SF) flag. The overflow flag is set if the result of an operation overflows (or underflows). The sign flag is set if the result of an operation is negative. If vleft = vright , the ZF is set (just as for

问题 This question is about the cmp instruction in assembly. I cannot understand how my books reasoning regarding the SF and OF flags. cmp vleft, vright According to my book: For signed integers, there are three flags that are important: the zero (ZF) flag, the overflow (OF) flag and the sign (SF) flag. The overflow flag is set if the result of an operation overflows (or underflows). The sign flag is set if the result of an operation is negative. If vleft = vright , the ZF is set (just as for

问题 I created simple code to load second sector from hard drive, and then write to whole screen, with spaces with red background. The problem is that always instead of spaces I got @ signs. This is the code: org 0x7C00 bits 16 xor ax,ax mov ds,ax mov es,ax mov bx,0x8000 cli mov ss,bx mov sp,ax sti cld clc xor ah,ah int 0x13 mov bx,0x07E0 mov es,bx xor bx,bx mov ah,0x2 ;function mov al,0x5 ;sectors to read mov ch,0x0 ;track mov cl,0x2 ;sector mov dh,0x0 ;head int 0x13 ;jc error ;mov ah, [0x7E00]

问题 An excerpt of Wikipedia's article on Physical Address Extension: x86 processor hardware-architecture is augmented with additional address lines used to select the additional memory, so physical address size increases from 32 bits to 36 bits. This, theoretically, increases maximum physical memory size from 4 GB to 64 GB. Along with an image explaining the mechanism: But I can't see how the address space is expanded from 4GB to 64GB. And 4 * 512 * 512 * 4K still equals 4GB, isn't it? 回答1: x86

问题 An excerpt of Wikipedia's article on Physical Address Extension: x86 processor hardware-architecture is augmented with additional address lines used to select the additional memory, so physical address size increases from 32 bits to 36 bits. This, theoretically, increases maximum physical memory size from 4 GB to 64 GB. Along with an image explaining the mechanism: But I can't see how the address space is expanded from 4GB to 64GB. And 4 * 512 * 512 * 4K still equals 4GB, isn't it? 回答1: x86

问题 I am creating a little bootloader+kernel and till now I managed to read disk, load second sector, load GDT, open A20 and enable pmode. I jumped to the 32-bits function that show me a character on the screen, using the video memory for textual content (0x000B0000 - 0x000B7777) pusha mov edi, 0xB8000 mov bl, '.' mov dl, bl mov dh, 63 mov word [edi], dx popa Now, I would like to go a little further and draw a single pixel on the screen. As I read on some website, if I want to use the graphics

问题 I am creating a little bootloader+kernel and till now I managed to read disk, load second sector, load GDT, open A20 and enable pmode. I jumped to the 32-bits function that show me a character on the screen, using the video memory for textual content (0x000B0000 - 0x000B7777) pusha mov edi, 0xB8000 mov bl, '.' mov dl, bl mov dh, 63 mov word [edi], dx popa Now, I would like to go a little further and draw a single pixel on the screen. As I read on some website, if I want to use the graphics

问题 I am creating a little bootloader+kernel and till now I managed to read disk, load second sector, load GDT, open A20 and enable pmode. I jumped to the 32-bits function that show me a character on the screen, using the video memory for textual content (0x000B0000 - 0x000B7777) pusha mov edi, 0xB8000 mov bl, '.' mov dl, bl mov dh, 63 mov word [edi], dx popa Now, I would like to go a little further and draw a single pixel on the screen. As I read on some website, if I want to use the graphics

问题 I am using 8086 emulator and DOSBOX and MASM. I know that when we multiply 8-bit with 8-bit, answer will be of 16-bit. al*(8-bit)=ax And when we multiply 16-bit with 16-bit,answer will of 32-bit. ax*(16-bit)=dx & ax But if the answer is in (dx & ax) and I want to multiply 8-bit or 16-bit number then it will simply perform with ax But I needed to multiply a number with answer in (dx & ax) . So how to overcome this problem? I need solve this situation for the factorial program. Where I am

问题 I know that -4 is copied into the EAX register. My doubts: -4 will be converted into two's complement binary notation before copying to EAX or not? If it is converted into two's complement binary notation , who does the job? Is there any special opcode for denoting negative numbers? What is the possible maximum negative number we can store in EAX register? Is there any special opcode or instructions for signed arithmetic? what happens when we multiply a negative and positive number in CPU?