warp-scheduler | 易学教程

cuda: warp divergence overhead vs extra arithmetic

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问题 Of course, warp divergence, via if and switch statements, is to be avoided at all costs on GPUs. But what is the overhead of warp divergence (scheduling only some of the threads to execute certain lines) vs. additional useless arithmetic? Consider the following dummy example: verison 1: __device__ int get_D (int A, int B, int C) { //The value A is potentially different for every thread. int D = 0; if (A < 10) D = A*6; else if (A < 17) D = A*6 + B*2; else if (A < 26) D = A*6 + B*2 + C; else D

cuda shared memory and block execution scheduling

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问题 I would like to clear up an execution state with CUDA shared memory and block execution based on the amount of shared memory used per block. State I target on GTX480 nvidia card which has 48KB shared memory per block and 15 streaming multiprocessors. So, if i declare a kernel with 15 blocks, each one uses 48KB of shared memory and no other restriction is reached (registers, maximum threads per block etc.) every block is running into one SM(of 15) until the end. In this case is needed only

Questions of resident warps of CUDA

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问题 I have been using CUDA for a month, now i'm trying to make it clear that how many warps/blocks are needed to hide the latency of memory accesses. I think it is related to the maximum of resident warps on a multiprocessor. According to Table.13 in CUDA_C_Programming_Guide (v-7.5),the maximum of resident warps per multiprocessor is 64. Then, my question is : what is the resident warp? is it refer to those warps with the data read from memory of GPUs and are ready to be processed by SPs? Or

How do CUDA blocks/warps/threads map onto CUDA cores?

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I have been using CUDA for a few weeks, but I have some doubts about the allocation of blocks/warps/thread. I am studying the architecture from a didactic point of view (university project), so reaching peak performance is not my concern. First of all, I would like to understand if I got these facts straight: The programmer writes a kernel, and organize its execution in a grid of thread blocks. Each block is assigned to a Streaming Multiprocessor (SM). Once assigned it cannot migrate to another SM. Each SM splits its own blocks into Warps (currently with a maximum size of 32 threads). All the

How do CUDA blocks/warps/threads map onto CUDA cores?

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问题 I have been using CUDA for a few weeks, but I have some doubts about the allocation of blocks/warps/thread. I am studying the architecture from a didactic point of view (university project), so reaching peak performance is not my concern. First of all, I would like to understand if I got these facts straight: The programmer writes a kernel, and organize its execution in a grid of thread blocks. Each block is assigned to a Streaming Multiprocessor (SM). Once assigned it cannot migrate to