system-verilog-assertions

问题 I have a serial output of a verilog module I'd like to testbench using system-verilog. The output, called 'SO' will output something like 8'hC6 given the correct serial input 'SI' with a value of say 8'h9A. Is there an easy way to encode / decode serial IOs without having to explicitly describe each signal? For example: assert property @(posedge clk) $rose(EN) |-> ##[1:3] SI ##1 !SI[*2] ##1 SI[*2] ##1 !SI ##1 SI ##1 !SI ##[1:3] SO[*2] ##1 !SO[*3] ##1 SO[*2] ##1 !SO; It looks like a jumbled

问题 I have a few assertions that use the triggered property of sequences. This is useful for checking properties of the form "when X happens, Y must have happened sometime in the past". Let's take a simple example: Given three signals, a , b and c , c is only allowed to go high if a was high 3 cycles ago and b was high 2 cycles ago. This is a trace that satisfies this property: To be able to check this, we'd need a helper (clocked) sequence that should match at the point where a c is legal:

问题 I met a problem when trying to write this assertion. I tried to assert the scenario that signal B must be true at least 1 occurrence after signal A is true. The assertion I wrote is below: example : assert property( @(posedge clk) disable iff(reset) A |-> ##[0:$] B[->1]) else `uvm_error(....) The problem is, if during the simulation signal B is never be true after A is true, the uvm_error is not executed. I expected it to be executed, and the simulation reports the message: example: started