risc

ARM处理器和体系结构介绍(Cortex-A9)

↘锁芯ラ 提交于 2019-12-21 18:07:29
ARM(Advanced RISC Machines) 概述 :有三种含义,它是一个公司的名称,是一类微处理器的通称,还是一种技术的名称。 技术特征 体积小、低功耗、低成本、高性能。 支持Thumb(16位)/ARM(32位)双指令集,能很好地兼容8/16位器件。 大量使用寄存器,指令执行速度更快。 大多数数据操作都在寄存器中完成。 寻址方式灵活简单,执行效率高。 指令长度固定。 嵌入式RISC微处理器 概述 :RISC(Reduced Instruction Set Computer)是精简指令集计算机,RISC把着眼点放在如何使计算机的结构更加简单和如何使计算机的处理速度更加快速上。RISC选取了使用频率最高的简单指令,抛弃复杂指令,固定指令长度,减少指令格式和寻址方式,不用或少用微码控制。 嵌入式CISC微处理器 概述 :传统的复杂指令级计算机(CISC)更侧重于硬件执行指令的功能性,使CISC指令及处理器的硬件结构更加复杂。 RISC和CISC的区别 ARM的基本数据类型 ARM采用32位架构,ARM的基本数据类型有以下3种。 Byte:字节,8bit。 Halfword:半字,16bit(半字必须与2字节边界对齐)。 Word:字,32bit(字必须与4字节边界对齐)。 注意 ARM 系统结构 v4 以上版本支持以上3种数据类型,v4 以前版本仅支持字节和字。

服务器硬件知识普及篇之服务器CPU

限于喜欢 提交于 2019-12-18 02:05:17
服务器是网络中的不可替代的重要设备,要接受少至几十人、多至成千上万人的访问,因此对服务器具有大数据量的快速吞吐、超强的稳定性、长时间运行等严格要求。所以说CPU是计算机的“大脑”,是衡量服务器性能的首要指标。 目前,服务器的CPU仍按CPU的指令系统来区分,通常分为CISC型CPU和RISC型CPU两类,后来又出现了一种64位的VLIM(Very Long Instruction Word超长指令集架构)指令系统的CPU。 服务器硬件知识普及篇之服务器CPU ​ ​ 一、CISC型CPU CISC是英文“Complex Instruction Set Computer”的缩写,中文意思是“复杂指令集”,它是指英特尔生产的x86(intel CPU的一种命名规范)系列CPU及其兼容CPU(其他厂商如AMD,VIA等生产的CPU),它基于PC机(个人电脑)体系结构。这种CPU一般都是32位的结构,所以我们也把它成为IA-32 CPU。(IA: Intel Architecture,Intel架构)。CISC型CPU目前主要有intel的服务器CPU和AMD的服务器CPU两类。 (1)intel的服务器CPU (2)AMD的服务器CPU 二、RISC型CPU RISC是英文“Reduced Instruction Set Computing ”的缩写,中文意思是“精简指令集”

How does MIPS I forward from EX to ID for branches without stalling?

北城以北 提交于 2019-12-17 20:51:45
问题 addiu $6,$6,5 bltz $6,$L5 nop ... $L5: Is that safe on MIPS I? If so, how? Original MIPS I is a classic 5-stage RISC IF ID EX MEM WB design that hides all of its branch latency with a single branch-delay slot by checking branch conditions early, in the ID stage. (Which is why it's limited to equal/not-equal, or sign-bit checks like lt or ge zero, not lt between two registers that would need carry-propagation through an adder.) Doesn't this mean that branches need their input ready a cycle

Direct Arithmetic Operations on Small-sized Numbers in RISC Architectures

徘徊边缘 提交于 2019-12-14 03:58:49
问题 Are there any RISC architectures which allow arithmetic operations to be applied individually to bytes, half-words and other data cells, whose size is less than the size of the CPU general purpose registers? In Intel x86 (IA-32) and x86-64 (known as EM64T or AMD64) processors not only the whole register is available, but its smaller parts are operable as well. Intel ISA allows to perform all the arithmetic operations on the whole register, it's half, quarter and a byte (to be more precise,

Indexed addressing mode and implied addressing mode

跟風遠走 提交于 2019-12-12 13:19:47
问题 Indexed addressing mode is usually used for accessing arrays as arrays are stored contiguosly. We have a index register which gets incremented in every iteration which when added to base address gives the array element address. I don't understand the actual need of this addressing mode. Why can't we do this with direct addressing ? We have the base address and we can just add 1 to it every time when accessing. Why do we need indexed addressing mode which has a overhead of index register ? I

Is processor can do memory and arithmetic operation at the same time?

浪子不回头ぞ 提交于 2019-12-12 12:22:49
问题 In the study of assembler and processor, one thing takes me out, how is done the instruction : add mem, 1 In my head, the processor cannot load the memory value and process the arithmetic operation during the same instruction. So I figure it takes place like: mov reg, mem add reg, 1 mov mem, reg If I consider a processor with a RISC Pipeline, we can observe some stalls. It's surprising for an instruction as simple as i++ : | Fetch | Decode | Exec | Memory | WriteB | | Fetch | | | Decode |

Example with MIPS, Pipelining and Branch Delay Slot

青春壹個敷衍的年華 提交于 2019-12-11 16:32:42
问题 I am preparing for a test and have such example. Following code: 1: SLL $1, $1, 2 2: LW $2, 1000($1) 3: BEQL $2, $0, END 4: ADDI $3, $2, 1 5: MULT $3, $2 6: MFLO $4 END: 7: J QUIT ... QUIT: 100: NOP is executed on RISC processor (with quasi MIPS instruction set) with five-stage pipeline no bypassing no dynamic scheduling Branch Delay Slot Additionally we know, that branch won't be taken My task is to understand how the Branch Delay Slot works in this situation and build the correct Pipeline

三种主流芯片架构

本秂侑毒 提交于 2019-12-11 06:03:29
三种主流芯片架构简单比较 三种主流芯片架构   1. ARM ARM是高级精简指令集的简称(Advanced RISC Machine),它是一个32位的精简指令集架构,但也配备16位指令集,一般来讲比等价32位代码节省达35%,却能保留32位系统的所有优势。 ARM处理器的主要特点是: (1)体积小、低功耗、低成本、高性能——ARM被广泛应用在嵌入式系统中的最重要的原因 支持Thumb(16位)/ARM(32位)双指令集,能很好的兼容8位/16位器件; (2)大量使用寄存器,指令执行速度更快; (3)大多数数据操作都在寄存器中完成; (4)寻址方式灵活简单,执行效率高; (5)指令长度固定。 (6)Load_store结构:在RISC中,所有的计算都要求在寄存器中完成。而寄存器和内存的通信则由单独的指令来完成。而在CSIC中,CPU是可以直接对内存进行操作的。 流水线处理方式。    2. MIPS MIPS架构(英语:MIPS architecture,为Microprocessor without interlocked piped stages architecture的缩写,亦为Millions of Instructions Per Second的相关语),是一种采取精简指令集(RISC)的处理器架构,1981年出现,由MIPS科技公司开发并授权

Why are there two ways to multiply arbitrary signed numbers in MIPS?

主宰稳场 提交于 2019-12-11 02:59:56
问题 If you need to multiply two arbitrary signed numbers in MIPS, is there a reason to prefer: mul $t0 $s0 $s1 Or this: mult $s0 $s1 mflo $t0 ? I'm finding inconsistent answers online with regard to what each one means. At first glance I would expect the former to be a pseudo-instruction for the latter. (And there's even a web page that claims that.) But looking at the machine code it appears that mult is a valid R-type instruction (opcode 0) whereas mul has a nonzero opcode (0x1c) and so shouldn

总有些莫名其妙的错误

[亡魂溺海] 提交于 2019-12-10 04:31:31
昨天晚上因为服务器机房电路检修,所有的服务器都停机。今天早上八点半就被电话吵醒,说是服务系统不能访问。赶紧的爬起来打开电脑,访问系统,出现错误ORA-12541:TNS:没有监听器。 赶紧的在网上搜索了一下解决办法,登陆数据库服务器,执行lsnrctl命令 $ lsnrctl start LSNRCTL for IBM/AIX RISC System/6000: Version 9.2.0.8.0 - Production on 10-MAY-2 008 09:27:08 Copyright (c) 1991, 2006, Oracle Corporation. All rights reserved. Starting /i2_dev/oracle/product/9.2/bin/tnslsnr: please wait... TNSLSNR for IBM/AIX RISC System/6000: Version 9.2.0.8.0 - Production Log messages written to /i2_dev/oracle/product/9.2/network/log/listener.log Listening on: (DESCRIPTION=(ADDRESS=(PROTOCOL=tcp)(HOST=i2arptest)(PORT=1521)))