page-tables

问题 I was doing Windows system programming and wondered if I can access a process' page table on source code level. Here is what I know about page table related to virtual memory. Let's suppose an user just runs a process called 'A' process on Windows OS(32bit). First of all, the OS creates and maintains 4GB virtual address space for A process. (2GB of it is Kernel address space and the other 2GB is User address space. Any codes in User address space cannot directly access Kernel address space.)

问题 I was doing Windows system programming and wondered if I can access a process' page table on source code level. Here is what I know about page table related to virtual memory. Let's suppose an user just runs a process called 'A' process on Windows OS(32bit). First of all, the OS creates and maintains 4GB virtual address space for A process. (2GB of it is Kernel address space and the other 2GB is User address space. Any codes in User address space cannot directly access Kernel address space.)

问题 I've been studying about paging and page tables. I don't see to understand where page tables are located. In one of the answers from stack exchange(https://unix.stackexchange.com/questions/487052/where-is-page-table-stored-in-linux), it is said that page tables are in kernel address space, which is in virtual memory(from what I understood). However in lecture slides from University of Illinois(https://courses.engr.illinois.edu/cs241/sp2014/lecture/09-VirtualMemory_II_sol.pdf), page tables

问题 I've been studying about paging and page tables. I don't see to understand where page tables are located. In one of the answers from stack exchange(https://unix.stackexchange.com/questions/487052/where-is-page-table-stored-in-linux), it is said that page tables are in kernel address space, which is in virtual memory(from what I understood). However in lecture slides from University of Illinois(https://courses.engr.illinois.edu/cs241/sp2014/lecture/09-VirtualMemory_II_sol.pdf), page tables

问题 I've been studying about paging and page tables. I don't see to understand where page tables are located. In one of the answers from stack exchange(https://unix.stackexchange.com/questions/487052/where-is-page-table-stored-in-linux), it is said that page tables are in kernel address space, which is in virtual memory(from what I understood). However in lecture slides from University of Illinois(https://courses.engr.illinois.edu/cs241/sp2014/lecture/09-VirtualMemory_II_sol.pdf), page tables

问题 I am doing a page table walk. When I am getting ready to update the kernel I get an error: kernel/sys.c: In function ‘__do_sys_get_page_info’: kernel/sys.c:2745:23: error: passing argument 1 of ‘pud_offset’ from incompatible pointer type [-Werror=incompatible-pointer-types] pud = pud_offset(pgd, vmpage); ^ In file included from ./include/linux/mm.h:99:0, from kernel/sys.c:19: ./arch/x86/include/asm/pgtable.h:905:22: note: expected ‘p4d_t * {aka struct <anonymous> *}’ but argument is of type

问题 I was reading the MDS attack paper RIDL: Rogue In-Flight Data Load. The set pages as write-back, write-through, write-combined or uncacheable and with different experiments determines that the Line Fill Buffer is the cause of the micro-architectural leaks. On a tangent: I was aware that memory can be uncacheable, but I assumed that cacheable data was always cached in a write-back cache, i.e. I assumed that the L1, L2 and LLC were always write-back caches. I read up on the differences between

问题 As far as I know, a memory access of CPU involves CPU cache and MMU. CPU will try to find its target in cache and if a cache miss happens, CPU will turn to MMU. During accessing by MMU, the accessed/dirty bit of correspondent page table entry will be set by hardware. However to the best of my knowledge, most CPU design won't trigger the MMU unless there's a cache miss, and here my problem is, will the accessed/dirty bit of page table entry still be set under a cache hit? Or it's architecture

问题 Closed . This question is opinion-based. It is not currently accepting answers. Want to improve this question? Update the question so it can be answered with facts and citations by editing this post. Closed 3 years ago . The ARM720T user manual mentions small and large pages. Since the ARM 720T requires a 64KB page table entry to be duplicated 16 times in the page table, why not place 16 small page (4KB) entries to mimic a 64KB page entry instead of using a large page in the first place? 回答1:

问题 I am trying to manually mark a certain memory region of a userspace process as non-cacheable (for educational purposes, not intended to be used in production code) by setting a flag in the respective page table entries. I have an Ubuntu 14.04 (ASLR disabled) with a 4.4 Linux kernel running on an x86_64 Intel Skylake processor. In my kernel module I have the following function: /* * Set memory region [start,end], excluding 'addr', of process with PID 'pid' as uncacheable. */ ssize_t set