SystemVerilog packed array vs unpacked array memory footprint
问题 Is it true that with the contemporary advanced SV RTL simulators, the simulation footprint may increase when using unpacked arrays vs the packed arrays? If so, is this a problem and do verification teams insist on rules to use packed arrays? TIA. Sanjay 回答1: "[Does] the simulation footprint may increase when using unpacked arrays vs the packed arrays?" It depends on the simulator allocates and accesses its memory. Most cases packed arrays will have a smaller memory footprint then unpacked