msr

I wrote a program which reads the APERF/MPERF counters on an Intel chip (page 2 on http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.pdf ). These counters are readable/writable via the readmsr/writemsr instructions, and I'm currently simply reading them at a regular interval via a device driver in Windows 7. The counters are 64 bits, and increment approximately with each processor clock, so you'd expect them to overflow in a very long amount of time, but when I read the counters, their value jumps around as if they are being reset by

I am getting Error while trying to disable Hardware prefetcher in my Core i7 system. I am following the method as per the link How do I programmatically disable hardware prefetching? In my system grep -i msr /boot/config-$(uname -r) CONFIG_X86_DEBUGCTLMSR=y CONFIG_X86_MSR=y CONFIG_SCSI_ARCMSR=m Here is my error message root@ ./rdmsr 0x1a0 850089 [root@ ./wrmsr -p 0 0x1a0 0x850289 (to disable hardware prefetcher in Core i7) wrmsr:pwrite: Input/output error I am getting same error for disabling Adjacent cache line prefetcher Any idea how to resolve this problem ? Thanks in advance . MSR

Is there some way to read the x86-64 model-specific registers, specifically IA32_FS_BASE and IA32_GS_BASE, while debugging a program using GDB? Less preferable would be a solution using a dynamic instrumentation package like Intel's Pintool, but it would be appreciated all the same. If you prefer not changing your code (or if the code is not available) you could do something similar to amdn's answer in the following way. The call to arch_prctl requires a pointer to a uint64_t, for which I use the address to an empty portion of the stack (8 bytes below the current stack pointer). After the call

I am trying to write a simple application that can read msr registers, and am running this application from userspace. I have loaded the msr module and given read permissions for everyone to /dev/cpu/*/msr. But still the user is not able to access these files but the root can. The permissions look like this: crw-r--r-- 1 root root 202, 0 sep 6 17:55 /dev/cpu/0/msr crw-r--r-- 1 root root 202, 1 sep 6 17:55 /dev/cpu/1/msr crw-r--r-- 1 root root 202, 2 sep 6 17:55 /dev/cpu/2/msr crw-r--r-- 1 root root 202, 3 sep 6 17:55 /dev/cpu/3/msr I keep getting "Operation not permitted" error message when I

Every modern high-performance CPU of the x86/x86_64 architecture has some hierarchy of data caches: L1, L2, and sometimes L3 (and L4 in very rare cases), and data loaded from/to main RAM is cached in some of them. Sometimes the programmer may want some data to not be cached in some or all cache levels (for example, when wanting to memset 16 GB of RAM and keep some data still in the cache): there are some non-temporal (NT) instructions for this like MOVNTDQA ( https://stackoverflow.com/a/37092 http://lwn.net/Articles/255364/ ) But is there a programmatic way (for some AMD or Intel CPU families