interrupt-handling

问题 I am reading the Intel Manual 3A Chapter 6 Interrupt and Exception Handling. Interrupt and Exception have 3 sources respectively. For Software-Generated Interrupt, it says: The INT n instruction permits interrupts to be generated from within software by supplying an interrupt vector number as an operand. For example, the INT 35 instruction forces an implicit call to the interrupt handler for interrupt 35. Any of the interrupt vectors from 0 to 255 can be used as a parameter in this

问题 How would I relocate the ARM exception vectors ? Basically, I need to be able to remap them in a way, so when the ARM core tries to execute the vector, it should execute the custom exception vector that is stored in kernel's RAM bit and not in the ROM that is at 0x0 . Is that possible? Or am I meant to route the interrupts to the kernel from the ROM ? So essentially, is there a way of telling the ARM core, " here is the new address for your vector table "? I know that you can start the CPU in

问题 I'm trying to understand how QEMU handles interrupts for ARM processors. I have a bare metal binary blob (ie, not linux -- just some assembly code) which was built for a ARM1176. When run in QEMU, during initialisation the code in the binary blob sets bit 13 of the CPSR indicating that the interrupt vector table is located at 0xFFFF0000 . Hooking up GDB and dumping the instructions at that address, I can indeed see the corresponding interrupt vector table. On an IRQ, it jumps to 0xFFFF0018 ,

问题 I heard printf() in C is not supposed to be used in ISR. Is it because it's a blocking call, or is it because it's not re-entrant? If printf() is not re-entrant, then wouldn't it means that it can not be used for multi-thread program as well, unless it's 'synchronized' in some way? Thanks, 回答1: I think it might be all of those, and more. Typical printf() implementations can do dynamic (heap) memory allocation, which is generally not the fastest thing to be doing, and might also have issues

问题 I'm building an IR to wifi bridge using an esp8266. Basically I'm building an IR receiver connected to an esp8266 inside an IR remote control, to forward received IR Remote keypresses over wifi to a server. I'm using a Wemos D1 Mini. I already have the IR decoding and network forwarding part working, but it is always on, which uses a lot of battery, especially considering that 99% of the time no buttons are being pressed. I want it to go into deep sleep when a button hasn't been pressed for a

问题 I'm building an IR to wifi bridge using an esp8266. Basically I'm building an IR receiver connected to an esp8266 inside an IR remote control, to forward received IR Remote keypresses over wifi to a server. I'm using a Wemos D1 Mini. I already have the IR decoding and network forwarding part working, but it is always on, which uses a lot of battery, especially considering that 99% of the time no buttons are being pressed. I want it to go into deep sleep when a button hasn't been pressed for a

问题 I read that the the Software generated interrupts in ARM are used as Inter-processor interrupts. I can also see that 5 of those interrupts are already in use. I also know that ARM provides 16 Software generated interrupts. In my application i am running a bare metal application on of the ARM-cortex cores and Linux on the other. I want to communicate some data from the core running bare metal application to the core which is running Linux. I plan to copy the data to the on chip memory ( which

问题 I'm trying to understand the system call interface and implementation in the Linux kernel. I know about entry.S and the relationship between libc headers and implementation. What I want to know is where in the kernel is the int 80h received for the first time i.e. the place that decides that it's actually the 80h interrupt. Can anyone point me to the LXR link for this please? 回答1: CONFIG_X86_32 arch/x86/kernel/entry_32.S:system_call (INT $0x80) arch/x86/kernel/entry_32.S:ia32_sysenter_target

问题 When we use irq_set_chained_handler the irq line will not be disabled or not, when we are servicing the associated handler, as in case of request_irq. 回答1: It doesn't matter how the interrupt was setup. When any interrupt occurred, all interrupts (for this CPU) will be disabled during the interrupt handler. For example, on ARM architecture first place in C code where interrupt handling is found is asm_do_IRQ() function (defined in arch/arm/kernel/irq.c ). It's being called from assembler code

问题 I made the following program for learning the behavior of SIG_SETMASK . The following program is supposed to block SIGINT the interrupt signal until the func() function calls sigprocmask(SIG_SETMASK,&fOnemask,NULL); where as fOnemask is empty cuz no signals were store in sigset before it. But as I call sigprocmask(SIG_SETMASK,&fTwoCmask,NULL); inside func2() function before returning,where fTwomask contains previous signal list made by func() function, the program starts receiving signals and