<<module name>> not a task or void function in verilog
问题 I am trying to create a module for carry select adder in verilog. Everything works fine except the following portion where it is causing compilation error. module csa(a,b,s,cout); input[15:0] a,b; output [15:0] s; output cout; wire zero_c1, zero_c2,zero_c3,zero_c4,zero_c5; wire one_c1, one_c2,one_c3,one_c4,one_c5; wire temp_c1,temp_c2,temp_c3,temp_c4,temp_c5; wire [15:0] s_zero, s_one; initial begin fork fa(s[0], temp_c1,a[0],b[0],0); fa_one(s_zero[1],s_one[1],zero_c1,one_c1,a[1],b[1]); fa