一.目的:使用DVE GUI调试现有的Verilog设计。 代码:fifo.v // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ // CDANOTE Verilog Synchronous FIFO // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ module fifo (clk, rstp, src_in, dst_in, data_in, writep, readp, src_out, dst_out, data_out, emptyp, fullp); input clk; input rstp; input [7:0] src_in; input [7:0] dst_in; input [31:0] data_in; input readp; input writep; output [7:0] src_out; output [7:0] dst_out; output [31:0] data_out; output emptyp; output fullp; // Defines sizes in terms of bits. // parameter DEPTH = 2, FULL = (1<<3