cortex-a | 易学教程

i.MX53 QSB and ARM TrustZone

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问题 I'm exploring the i.MX53 QSB and the TrustZone extensions. I run an OS in the secure world thanks to the U-Boot bootloader. Now I'm in the secure world. I have three questions : The first question is when should I share the memory and the interrupts between the secure and normal world ? The second one is how can I move to the normal world in order to run a Rich OS on it? The third question concerns the monitor mode code, where should I write it ? Is it a kernel module in the secure world ?

Why does my SWI instruction hang? (BeagleBone Black, ARM Cortex-A8 cpu)

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问题 I'm starting to write a toy OS for the BeagleBone Black, which uses an ARM Cortex-A8-based TI Sitara AM3359 SoC and the U-Boot bootloader. I've got a simple standalone hello world app writing to UART0 that I can load through U-Boot so far, and now I'm trying to move on to interrupt handlers, but I can't get SWI to do anything but hang the device. According to the AM335x TRM (starting on page 4099, if you're interested), the interrupt vector table is mapped in ROM at 0x20000. The ROM SWI

Why does my SWI instruction hang? (BeagleBone Black, ARM Cortex-A8 cpu)

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I'm starting to write a toy OS for the BeagleBone Black , which uses an ARM Cortex-A8-based TI Sitara AM3359 SoC and the U-Boot bootloader. I've got a simple standalone hello world app writing to UART0 that I can load through U-Boot so far, and now I'm trying to move on to interrupt handlers, but I can't get SWI to do anything but hang the device. According to the AM335x TRM (starting on page 4099, if you're interested), the interrupt vector table is mapped in ROM at 0x20000. The ROM SWI handler branches to RAM at 0x4030ce08, which branches to the address stored at 0x4030ce28. (Initially, this

Why is the reset handler located at 0x0 for Cortex-A but not for Cortex-M3

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问题 What is the reason Cortex-M3 has the initial stack pointer value located at 0x0, and reset handler located at 0x4? What is the design justification for this? Why couldn't the ARM guys leave 0x0 to the reset handler like they do for Cortex-A, then initialize SP inside the reset handler? 回答1: I think this one falls under the "it's not a bug, it's a feature" banner. The ARM architecture M (microcontroller) profile has a completely different exception model to the A and the R profiles. The A

Domain in arm architecture means what

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问题 When I debug MMU in Cortex-A9 MPCore, I always see Domain Access Control Register , but, what does domain means ? up to 16 domains ? Anyone can give me a link to explain this ? 回答1: TL;DR The DACR not only decreases the context switch code path, but can also speed execution after the context switch occurs. There are several links which explain the specifics of Domain Access Control Register or DACR . For example ARM's Memory access permissions and domains. However, this page and many others

Load 8bit uint8_t as uint32_t?

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my image processing project works with grayscale images. I have ARM Cortex-A8 processor platform. I want to make use of the NEON. I have a grayscale image( consider the example below) and in my alogorithm, I have to add only the columns. How can I load four 8-bit pixel values in parallel, which are uint8_t , as four uint32_t into one of the 128-bit NEON registers? What intrinsic do I have to use to do this? I mean: I must load them as 32 bits because if you look carefully, the moment I do 255 + 255 is 512, which can't be held in a 8-bit register. e.g. 255 255 255 255 ......... (640 pixels) 255

Load 8bit uint8_t as uint32_t?

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问题 my image processing project works with grayscale images. I have ARM Cortex-A8 processor platform. I want to make use of the NEON. I have a grayscale image( consider the example below) and in my alogorithm, I have to add only the columns. How can I load four 8-bit pixel values in parallel, which are uint8_t , as four uint32_t into one of the 128-bit NEON registers? What intrinsic do I have to use to do this? I mean: I must load them as 32 bits because if you look carefully, the moment I do 255

ARM: Start/Wakeup/Bringup the other CPU cores/APs and pass execution start address?

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I've been banging my head with this for the last 3-4 days and I can't find a DECENT explanatory documentation (from ARM or unofficial) to help me. I've got an ODROID-XU board (big.LITTLE 2 x Cortex-A15 + 2 x Cortex-A7) board and I'm trying to understand a bit more about the ARM architecture. In my "experimenting" code I've now arrived at the stage where I want to WAKE UP THE OTHER CORES FROM THEIR WFI (wait-for-interrupt) state. The missing information I'm still trying to find is: 1. When getting the base address of the memory-mapped GIC I understand that I need to read CBAR; But no piece of

ARM: Start/Wakeup/Bringup the other CPU cores/APs and pass execution start address?

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问题 I've been banging my head with this for the last 3-4 days and I can't find a DECENT explanatory documentation (from ARM or unofficial) to help me. I've got an ODROID-XU board (big.LITTLE 2 x Cortex-A15 + 2 x Cortex-A7) board and I'm trying to understand a bit more about the ARM architecture. In my "experimenting" code I've now arrived at the stage where I want to WAKE UP THE OTHER CORES FROM THEIR WFI (wait-for-interrupt) state. The missing information I'm still trying to find is: 1. When