cortex-m

问题 I want to delay an ARM Cortex M0+ for n cycles, without using a timer, with the smallest possible code size. (I think this mandates use of assembly.) A delay of 0 cycles is simple no code. A delay of 1 cycle is a single NOP. A delay of 2 cycles is two NOPs. At what point is it (code-size) efficient to start looping? How many cycles does the tightest possible loop take? What is the setup time? Post answer notes: The following C code: register unsigned char counter = 100; while (counter-- > 0)

问题 My guess is that the __no_operation() intrinsic (ARM) instruction should take 1/(168 MHz) to execute, provided that each NOP executes in one clock cycle, which I would like to verify via documentation. Is there a standard location for information regarding the instruction cycle execution time for a processor? I am trying to determine how long an STM32f407IGh6 processor should take to execute a NOP instruction running at 168 MHz. Some processors require multiple oscillations per instruction

问题 I'm trying to write a multi-threaded bare-metal application for the STM32F4Discovery using the Real-Time For the Masses (RTFM) crate. I've frankensteined together a minimal application from an example for the STM32F3Discovery board and this example: #![deny(unsafe_code)] #![no_main] #![no_std] extern crate cortex_m; extern crate cortex_m_rtfm as rtfm; extern crate cortex_m_semihosting; extern crate panic_semihosting; extern crate stm32f4; use stm32f4::stm32f407; use rtfm::app; app! { device:

问题 I used to compile my microcontroller code with arm-none-eabi-gcc/arm-none-eabi-g++ and everything worked fine. I use the homebrew Cask gcc-arm-embedded on Mac. Yesterday I updated it and now I get these error messages for every object file at the link stage when I compile for a Cortex M4 architecture (compiles fine with M3): /usr/local/Caskroom/gcc-arm-embedded/6-2017-q1-update/gcc-arm-none-eabi-6-2017-q1-update/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/bin/ld: error:

问题 My question is about some popular but not well documented code I have found in ARM CORTEX M startup files like this STM32. The 'pattern' is: .size X,.-X ,where X is a symbol or label. I have found this answer and understand how .size directive and dot special symbol work, but still complete line seems to do nothing to me. The result of the operation .-X isn't stored anywhere. Could anybody explain what the line does? 回答1: That is placed at the end of function X, and the size of the function

问题 My project has started experiencing a problem in which the SysTick rate is usually, but not always set too fast. I have not changed the code that is relevant, and it seems to be temperature-related. I am using an STM32F072B-DISCOVERY board, with VisualGDB on Visual Studio Community 2015. My initialization code includes the following function: void Setup_Init_Clocks() { // Set up 48 MHz Core Clock using HSI (8Mhz) with PLL x 6 RCC_PLLConfig(RCC_PLLSource_HSI, RCC_PLLMul_6); RCC_PLLCmd(ENABLE);

问题 Update 2016-12 There is now also a minimal example for this behavior: https://community.nxp.com/message/862676 I'm using a ARM Cortex M4 with freertos using freescales freedom Kinetis IDE (gnu arm toolchain). Problem is that try { throw 4; // old scenario also not working: throw std::runtime_error("wut"); } catch (...) { } results in a halted CPU and code after the try or (when some is added) in the catch handler is not executed. And assembly can be found here: https://gist.github.com

问题 I am using arm-none-eabi-gcc toolchain, v 4.8.2, on LinuxMint 17.2 64b. I am, at hobbyist level, trying to play with a TM4C123G board and its usual features (coding various blinkies, uart things...) but always trying to remain as close to the metal as possible without using other libraries (eg CMSIS...) whenever possible. Also no IDE (CCS, Keil...), just Linux terminal windows, the board and I... All that mostly for education purpose. The issue : I am stuck trying to implement the usual

问题 I'm trying to understand why some Cortex-M0 code behaves differently when it is linked versus unlinked. In both cases it is loaded to 0x20000000 . It looks like despite my best efforts to generate position independent code by passing -fPIC to the compiler, the bl instruction appears to differ after the code has passed through the linker. Am I reading this correctly, is that just a part of the linker's job in ARM Thumb, and is there a better way to generate a position independent function call

问题 I don't get why I can't write mov r1, #5000 . Why I have to use ldr instead? R1 is 32 bit register and 5000 fits in range. And as I discovered I can mov r1, #255 but can't mov r1, #256 . It seems weird for me. 回答1: read the documentation on the instructions, in this context the instructions are fixed length, so you dont have room for both the instruction information (opcode, etc) and a 32 bit immediate in the 16 or 32 bit instruciton, not possible so some limitation on the immediate is