Solving Metastability Using Double-Register Approach
For solving metastability caused by different clock domains in Verilog, double-register method is used. But as far as I know, the final output of metastability is undetermined. Output is independent of input. So, my question is how to guarantee the correctness of output using double-register method? Thanks. You cannot be completely sure that you avoided metastability. As you mentioned, the output of a metastable flip-flop is unpredictable so you can potentially propagate a wrong value when you have metastability even with the 'two-register' approach. This method however never intended to solve