armv8

Does Clang lack CRC32 for ARMv8/Aarch64?

怎甘沉沦 提交于 2020-01-15 03:50:06
问题 I'm attempting to set-up CI for our Xcode cross-compiles. The cross-compiles test both ARMv7 and ARMv8. Things look good except when it comes time to link for ARMv8: clang++ -DNDEBUG -g2 -O3 -fPIC -pipe -Wall -miphoneos-version-min=7 -arch arm64 \ -isysroot /Applications/Xcode.app/Contents/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS10.2.sdk \ -stdlib=libc++ -c cryptlib.cpp clang++ -DNDEBUG -g2 -O3 -fPIC -pipe -Wall -miphoneos-version-min=7 -arch arm64 \ -isysroot

What gdb commands should I use to narrow down where in label 'main' did I get the segmentation fault?

坚强是说给别人听的谎言 提交于 2019-12-20 07:37:47
问题 Here's my assembly code and my main subroutine. Here are my macros and constants: .text fmt: .string "x \t\t ln(x)\n" sfmt: .string "%.10lf \t %.10lf\n" error: .string "Error" filename: .string "input.bin" .data LIM: .double 0r1.0E-13 zero: .double 0r0.0 one: .double 0r1.0 half: .double 0r0.5 define(i_r,w19) define(j_r,w20) define(n_r,w21) define(fd_r,w22) define(ln_x,d8) define(cur_term,d24) define(n_read,x25) define(x_j,d26) BUF_SIZE = 98*8 AT_FDCWD = -100 O_RDONLY = 0 buf_s = 16 .bss x_arr

How to determine ARMv8 features at runtime on iOS?

人盡茶涼 提交于 2019-12-18 03:09:12
问题 I am trying to determine when optional ARMv8 cpu features are available on iOS at runtime. On OS X desktops, like i686, x86_64, PPC and PPC64 we can use sysctl . See, for example, PR 3108, SIGILL-free processor capabilities detection on MacOS X. The "SIGILL-free processor capabilities" part is important because SIGILL -based feature probes corrupt memory on Apple platforms. At least three projects I follow have had problems with it, including Crypto++ and OpenSSL. Another part of the problem

Flush/Invalidate range by virtual address; ARMv8; Cache;

允我心安 提交于 2019-12-11 07:28:48
问题 I'm implementing cache maintenance functions for ARMv8 (Cortex-A53) running in 32 bit mode. There is a problems when I try to flush memory region by using virtual addresses (VA). DCacheFlushByRange looks like this // some init. // kDCacheL1 = 0; kDCacheL2 = 2; while (alignedVirtAddr < endAddr) { // Flushing L1 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r"(kDCacheL1) :); // select cache isb(); asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r"(alignedVirtAddr) :); // clean & invalidate dsb()