问题
Okay this question is more of a discussion . I have this project of implementing a pipelined MIPS processor in VHDL .
I am fully acquainted with the concepts of pipelining but I have never implemented it with VHDL . What are some good resources to learn implementation of pipelined processors in VHDL .
I need a head start ?
回答1:
There's a book Digital Design and Computer Architecture by David Harris and Sarah Harris. See Chapter 7 on Microarchitecture. 7.5 talks about pipelining using a MIPS processor model. 7.6 shows Verilog and VHDL code implementing. It's a textbook and there's a second edition, where the HDL examples from the companion web site are VHDL and SystemVerilog apparently. Looking through the VHDL code there doesn't appear to be emphasis on pipeline registers, rather on building blocks. The figures in 7.5 should be a big help and can be downloaded from the companion site as well.
On the opencores website there's the Ion - MIPS(tm) compatible CPU :: Overview, where you can download the VHDL model (after registering) for an R3000 compatible core. The pipeline stages are apparent in mips_cpu.vhdl, with names preceded by their pipeline stage (e.g. p1_alu_flags). There are testbenches for exercising the model and it's parts. There's information on tools so you can generate software to run on it.
There's GeorgiaTech's ECE 3055a course (see EE 3055 Outline in 2000 where 4 weeks was devoted to Pipelining. If you look at the Lab-2 Help, the exercise is to add pipelining into an RTL model in VHDL. The first stage is shown. What you can get out of this is that you can add pipelining to a behavior model, implied in the book above, as well. You can download the VHDL Synthesis Models (try MIPSSYN.TAR). The instruction simulator referred to can be found here: Index of ftp://ftp.cs.wisc.edu/pub/spim/. A description of Laboratory Assignment 2 is also available. Google is just full of clues on this and the MIPS model was described in A VHDL Synthesis Model of the MIPS Processor for use in Computer Architecture Laboratories. The Home page ECE 3055 Computer Architecture and Operating Systems J. Hamblen. See The Home page 32-bit MIPS VHDL Model for a set of files used in the class used with Altera tools. Contains the VHDL source code. The instruction simulator would be used in verification.
回答2:
Start by drawing a picture of the hardware you want.
If you already know VHDL and know a limited set of coding templates such as Logic gates (and, or, not, xor), adders (+), multipliers (*), Multiplexor (think case statement), Statemachine, and flip-flop you are all set. Make sure to learn the peculiarities of the operator result sizing - see VHDL Math Tricks of the Trade for help at: http://www.synthworks.com/papers
Next code your picture. Write a process or assignment for each piece in your hardware picture and connect them together with signals.
The one process stuff and using variables that some prefer is just a refinement. Get your project done now. Focus on refinement and determining your favorite coding style later. Even now my coding style is still evolving. Accept that it will never be perfect. Code is not art. Done and brute force is better than elegant and still debugging. P.S. Variables are fine. For some though they make it harder to see the hardware implications, so I don't recommend them for getting started. If you find them easy, go for it - but don't say I did now caution you.
Understand that synthesis tools are fussy about coding styles for hardware creation. So simulate and synthesize each block as you go so you learn both what works in simulation and synthesis - that way at the end you do not have lots of corrections during synthesis.
来源：https://stackoverflow.com/questions/17599960/project-on-mips-pipelined-processor