What is the difference between == and === in Verilog?

问题

What is the difference between:

if (dataoutput[7:0] == 8'bx) begin

and

if (dataoutput[7:0] === 8'bx) begin 

After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)

回答1:

Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z.

With the "case equality" operator, ===, x's are compared, and the result is 1.

With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators":

For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, then the result shall be a 1-bit unknown value (x).

回答2:

In Verilog:

• == tests logical equality (tests for 1 and 0, all other will result in x)
• === tests 4-state logical equality (tests for 1, 0, z and x)

回答3:

== For comparing bits (0 or 1) === For comparing all 4 states (0, 1, x, z)

== can be synthesized into a hardware (x-nor gate), but === can't be synthesized as x is not a valid logic level in digital, it is infact having voltages in between 0 and 1. And z is not itself any logic, it shows disconnection of the circuit.

来源：https://stackoverflow.com/questions/5927615/what-is-the-difference-between-and-in-verilog